Following a Signal Trail - NB2DSK01 Constraint Example

Frozen Content

Perhaps the most useful way to illustrate the NB2DSK01 constraint system is by example. To highlight the mapping involved between each constituent part of the system, we will follow the trail of a couple of example signals, related to the video output resource on the peripheral board PB01:

  • VGA_VSYNC
  • VGA_HSYNC

Let us assume that the NanoBoard system is comprised of the following:

  • A Desktop NanoBoard NB2DSK01 (revision 8)
  • A Xilinx Spartan-3 daughter board, DB30 (revision 6)
  • An Audio / Video peripheral board, PB01 (revision 7) – attached to the motherboard using the 'PERIPHERAL BOARD C' connector.

After using the auto-configuration feature (see NB2DSK01 - Configuring an FPGA Project Automatically), the configuration NB2DSK01_08_DB30_06 will be created, along with the following assigned constraint files:

  • NB2DSK01.08.Constraint
  • DB30.06.Constraint
  • PB01.07.Constraint
  • NB2DSK01_08_DB30_06_BoardMapping.Constraint

The following sections take a closer look at each of these constraint files, while at the same time keeping track of our two example signals, as they are mapped from the PB01 to the physical pins of the FPGA device on the DB30.

Peripheral Board Constraint File

The PB01.07.Constraint file defines the peripheral board:

Record=Constraint | TargetKind=PCB | TargetId=PB01.07 | Image=PB01.07 | ImageOffsetX=10 | ImageOffsetY=13 | Description=Audio/Video Peripheral Board

its connector:

Record=Constraint | TargetKind=Connector | TargetId=HDR1

and the mapping of on-board resource signals to that connector. For our example signals, the entries in the file appear as:

Record=Constraint | TargetKind=Port | TargetId=VGA_VSYNC | ConnectTo=HDR1-100
Record=Constraint | TargetKind=Port | TargetId=VGA_HSYNC | ConnectTo=HDR1-98

Peripheral Board-to-Motherboard Interface Mapping

The NB2DSK01_08_DB30_06_BoardMapping.Constraint file contains information that is used to map the peripheral board to one of the peripheral board connectors on the NB2DSK01 motherboard. The file and its content is created on-the-fly, based on the actual physical location of the peripheral board (in our example, attached to the motherboard using the 'PERIPHERAL BOARD C' connector).

The file includes a declaration for the motherboard and peripheral board instances:

Record=Constraint | TargetKind=PCBInstance | TargetId=NB2DSK01_08 | PCB=NB2DSK01.08
Record=Constraint | TargetKind=PCBInstance | TargetId=PB01_07     | PCB=PB01.07

and the connector mapping between the two:

Record=Constraint | TargetKind=ConnectorMap | TargetId=PB01_07.HDR1 | ConnectTo=NB2DSK01_08.EXT_C
 

The PCB instance and connector names for the peripheral board and motherboard are the same as those defined in the PB01.07.Constraint and NB2DSK01.08.Constraint files respectively.

 
With regard to our two example signals (VGA_VSYNC, VGA_HSYNC), we can see that they have left the peripheral board (HDR1-100 and HDR1-98) and are now available on the motherboard's 'PERIPHERAL BOARD C' connector (EXT_C-100 and EXT_C-98).

Motherboard Constraint File

The NB2DSK01.08.Constraint file declares the NanoBoard:

Record=Constraint | TargetKind=PCB | PCB=NB2DSK01.08 | Image=NB2DSK01.08

the plug-in boards:

Record=Constraint | TargetKind=PlugIn | TargetId=DB    | IdIndex=1 | ImageOffsetX=423 | ImageOffsetY=225 | ImageRotation=0
Record=Constraint | TargetKind=PlugIn | TargetId=EXT_A | IdIndex=2 | ImageOffsetX=17  | ImageOffsetY=254 | ImageRotation=0
Record=Constraint | TargetKind=PlugIn | TargetId=EXT_B | IdIndex=3 | ImageOffsetX=183 | ImageOffsetY=254 | ImageRotation=0
Record=Constraint | TargetKind=PlugIn | TargetId=EXT_C | IdIndex=4 | ImageOffsetX=323 | ImageOffsetY=217 | ImageRotation=180

its connectors:

Record=Constraint | TargetKind=Connector | TargetId=HDR_T | PlugIn=DB | Index=0
Record=Constraint | TargetKind=Connector | TargetId=HDR_B | PlugIn=DB | Index=1
Record=Constraint | TargetKind=Connector | TargetId=HDR_L | PlugIn=DB | Index=2
Record=Constraint | TargetKind=Connector | TargetId=EXT_A | PlugIn=EXT_A
Record=Constraint | TargetKind=Connector | TargetId=EXT_B | PlugIn=EXT_B
Record=Constraint | TargetKind=Connector | TargetId=EXT_C | PlugIn=EXT_C
Record=Constraint | TargetKind=Connector | TargetId=USER_A
Record=Constraint | TargetKind=Connector | TargetId=USER_B

and the peripheral board connector-to-daughter board connector pin mapping. For our two signals we've been tracking, which arrive at EXT_C pin 100 (VGA_VSYNC) and EXT_C pin 98 (VGA_HSYNC), the constraint file entries appear as:

Record=Constraint | TargetKind=Connection | TargetId=EXT_C-100 | ConnectTo=HDR_T-2
Record=Constraint | TargetKind=Connection | TargetId=EXT_C-98  | ConnectTo=HDR_T-4

This constraint file also contains the mapping of resources local to the motherboard, to pins of the daughter board connectors, for example:

Record=Constraint | TargetKind=Port | TargetId=CAN_TXD | ConnectTo=HDR_T-16
Record=Constraint | TargetKind=Port | TargetId=CAN_RXD | ConnectTo=HDR_T-14

Daughter Board-to-Motherboard Interface Mapping

The NB2DSK01_08_DB30_06_BoardMapping.Constraint file is again used to map the docking connectors on the daughter board to the corresponding connectors on the NB2DSK01 motherboard.

The file includes a declaration for the motherboard and daughter board instances:

Record=Constraint | TargetKind=PCBInstance | TargetId=NB2DSK01_08 | PCB=NB2DSK01.08
Record=Constraint | TargetKind=PCBInstance | TargetId=DB30_06     | PCB=DB30.06

and the connector mapping between the two:

Record=Constraint | TargetKind=ConnectorMap | TargetId=DB30_06.HDR_B | ConnectTo=NB2DSK01_08.HDR_B
Record=Constraint | TargetKind=ConnectorMap | TargetId=DB30_06.HDR_L | ConnectTo=NB2DSK01_08.HDR_L
Record=Constraint | TargetKind=ConnectorMap | TargetId=DB30_06.HDR_T | ConnectTo=NB2DSK01_08.HDR_T
 

The PCB instance and connector names for the daughter board and motherboard are the same as those defined in the DB30.06.Constraint and NB2DSK01.08.Constraint files respectively.

Daughter Board Constraint File

The DB30.06.Constraint file defines the daughter board:

Record=Constraint | TargetKind=PCB | TargetId=DB30.06 | Image=DB30.06 | ImageOffsetX=58 | ImageOffsetY=131 | Description=Xilinx Spartan 3 XC3S1500-FG676C

its physical FPGA device:

Record=Constraint | TargetKind=Part | TargetId=XC3S1500-4FG676C

its connectors:

Record=Constraint | TargetKind=Connector | TargetId=HDR_T | Index=0
Record=Constraint | TargetKind=Connector | TargetId=HDR_B | Index=1
Record=Constraint | TargetKind=Connector | TargetId=HDR_L | Index=2

and the mapping from pins of those connectors to pins of the physical FPGA device. For our two signals we've been tracking, which arrive at HDR_T pin 4 (VGA_HSYNC) and HDR_T pin 2 (VGA_VSYNC), the constraint file entries appear as:

Record=Constraint | TargetKind=Connection | TargetId=HDR_T-4 | FPGA_PINNUM=A8
Record=Constraint | TargetKind=Connection | TargetId=HDR_T-2 | FPGA_PINNUM=B8

This constraint file will also contain the mapping of resources local to the daughter board, and which are available for use by the FPGA design. For the Xilinx Spartan-3 daughter board, DB30, this includes the various on-board memories, for example:

Record=Constraint | TargetKind=Port | TargetId=BUS_RAM_NCS | FPGA_PINNUM=E12 | FPGA_SLEW=FAST
Record=Constraint | TargetKind=Port | TargetId=BUS_NWE     | FPGA_PINNUM=L25 | FPGA_SLEW=FAST
Record=Constraint | TargetKind=Port | TargetId=BUS_NOE     | FPGA_PINNUM=B19 | FPGA_SLEW=FAST

Overall Mapped Signal Path

By following the system's elemental constraint files in the correct sequence, we can easily piece together the full mapped signal path from any resource – on a peripheral board, the motherboard, or a daughter board – to the physical pin on the applicable daughter board's FPGA device.

Table 1 summarizes the generic sequence of constraint files used to follow a signal, depending on where the corresponding resource is located.

Table 1. Constraint file sequences used to obtain fully mapped signal path.
For a resource located on...
Use the following constraint file sequence to obtain fully mapped signal path...

Peripheral Board

Peripheral Board – Board Mapping – NB2DSK01 – Board Mapping – Daughter Board

NB2DSK01 Motherboard

NB2DSK01 – Board Mapping – Daughter Board

Daughter Board

Daughter Board

The specific peripheral board and daughter board constraint files used will depend on the peripheral board on which a resource resides, and the daughter board plugged into the NB2DSK01 motherboard. The Board Mapping constraint file generated is dependent on the boards used in your NanoBoard system.

For our underlying example used in the previous sections, the video resource is located on a peripheral board, meaning that the two signals under study pass through all four constraint files before ultimately arriving at the pins of the FPGA device. Figure 1 illustrates graphically, the overall path for these two signals, in terms of the relevant constraint files that they pass through.


Figure 1. Fully mapped signal paths for the example signals (VGA_HSYNC and VGA_VSYNC).

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