EP2C35F672C8 - Supported Pseudo-Differential IO Standards
The following table lists the pseudo-differential I/O standards supported by the EP2C35F672C8 device. Pseudo-differential outputs involve using two single-ended outputs, with the second inverted. Pseudo-differential inputs simply treat differential inputs as single-ended inputs, with only one input being decoded.
Table 1. Supported pseudo-differential I/O standards.
| I/O Standard | Description |
|---|---|
| Differential HSTL-15 class I | Differential High-Speed Transceiver Logic (1.5V) Class I |
| Differential HSTL-15 class II | Differential High-Speed Transceiver Logic (1.5V) Class II |
| Differential HSTL-18 class I | Differential High-Speed Transceiver Logic (1.8V) Class I |
| Differential HSTL-18 class II | Differential High-Speed Transceiver Logic (1.8V) Class II |
| Differential SSTL-18 class I | Differential Stub Series Terminated Logic (1.8V) Class I |
| Differential SSTL-18 class II | Differential Stub Series Terminated Logic (1.8V) Class II |
| Differential SSTL-2 class I | Differential Stub Series Terminated Logic (2.5V) Class I |
| Differential SSTL-2 class II | Differential Stub Series Terminated Logic (2.5V) Class II |
For more detailed information, refer to the Cyclone II Device Handbook (cyc2_cii5v1.pdf) available at www.altera.com.