Daughter Board Common Services

In addition to the user-available IO, the daughter board connectors on the NB2DSK01 motherboard provide pins for a series of other functions, including implementation of the NanoTalk communications protocol, power, and programming of the FPGA device. The following sections detail these additional signals, in relation to the daughter board connectors on the motherboard.

Hard JTAG Signals

All daughter board devices that are JTAG-equipped are connected to signals FPGA_TMS, FPGA_TCK, FPGA_TDI and FPGA_TDO. This allows the NB2DSK01 and Altium Designer to address the daughter board hardware using the JTAG protocol.

Soft JTAG Signals

Four FPGA I/O pins are reserved for JTAG signals that are utilized by the FPGA design. Altium Designer uses JTAG IP to communicate directly with the FPGA fabric, allowing applications to be debugged live. These signals (NEXUS_TMS, NEXUS_TCK, NEXUS_TDI and NEXUS_TDO) are derived in the NB2DSK01's NanoTalk Controller, which is implemented in a Xilinx Spartan-3 on the motherboard.

Daughter Board Identification Signals

FPGA devices from different manufacturers and families require differing auto-configuration processes, so it is necessary for the NanoTalk Controller to be able to identify the device family.

For 2-connector daughter boards, four signals (FPGA_ID0..FPGA_ID3) are hardwired on the daughter board to provide the required identification to the NanoTalk Controller. These four signals are also used on 3-connector daughter boards, to satisfy compatibility requirements when plugging such a daughter board into a NanoBoard-NB1 motherboard.

Enhanced identification is available on 3-connector daughter boards, courtesy of a 1-Wire® compatible slave memory device. This device carries more than enough storage capacity to hold information such as Board ID, physical Device ID, board revision, and so on. The NanoTalk Controller interrogates this device over a single wire, the associated signal of which is
ONE_WIRE_DBID.

SPI Bus Interface

The NB2DSK01 SPI system involves a variety of SPI-compatible slave resources, located across the hardware system – on the NB2DSK01 motherboard itself and also on certain peripheral boards that plug in to the motherboard. These SPI resources are accessible by three distinct SPI masters:

• Altium Designer (via the USB or parallel connection)

• The firmware – more specifically a TSK3000A processor therein – loaded onto the motherboard's Spartan-3 FPGA device (the NanoTalk Controller)

• The design loaded onto the currently plugged-in daughter board FPGA device.

Providing the required SPI bus arbitration between the masters, and access to the SPI devices, is the NB2DSK01's SPI Controller. The Controller, which is part of the NanoBoard firmware, plays the role of multiplexer/router – determining which master has access to the SPI bus and which SPI slave device is selected for communications.

From an FPGA design perspective, the NB2DSK01's SPI Controller provides an SPI path from the daughter board to each of the SPI slave resources resident in the system.

Daughter board connector signals DAU_SPI_DIN, DAU_SPI_DOUT, DAU_SPI_CLK, DAU_SPI_SEL and DAU_SPI_MODE provide this connectivity. During operation, the daughter board FPGA design communicates with the NB2DSK01's SPI Controller to establish a path between the design and a specific motherboard/peripheral board SPI device.

1-Wire® Bus Interface

A 1-Wire serial bus interface signal is provided (ONE_WIRE_DB_PB) which is connected through to each of the NB2DSK01's peripheral board connectors. This provides the ability to communicate directly from a processor in an FPGA design, with one or more slave 1-Wire compatible devices located across plugged-in peripheral boards (where such devices exist). As the 1-Wire bus is made available to all three peripheral board sites it allows development of a dedicated network of 1-Wire devices – a micro-LAN if you will.

Daughter Board Power Signals

Daughter board connectors HDR_T1 and HDR_B1 provide three power supplies to the daughter board, as well as ground signals. The power supply voltages are 5V, 3.3V and a third programmable supply, VCCX, providing an internal voltage for the target FPGA. The programmable voltage signal is daughter board dependent. It is supplied by a voltage regulator (designated U10), which is controlled by a reference voltage, VCCX_REF, supplied by the FPGA.
 

 
Current monitoring is in place on both the 5V and 3.3V power lines.
 

Daughter Board FPGA Control Signals

Daughter board connector HDR_T1 handles various signals between the NanoTalk Controller and the daughter board FPGA device, that are used to control that device. Such signals include detection of an FPGA device when a daughter board is plugged-in to the motherboard, as well as signals used to actually program the device with an FPGA design.

See Also