WB_USB - Pin Description

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Modified by Admin on Nov 6, 2013

The following pin description is for the WB_USB when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_USB pin description.

Name	Type	Polarity/ Bus size	Description
Control Signals
CLK_I	I	Rise	External (system) clock signal
RST_I	I	High	External (system) reset
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_USB (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
ADR_I	I	5	Address bus. Determines one of the following activities with the CY7C68001 device: "00000" – access FIFO 2 "00001" – access FIFO 4 "00010" – access FIFO 6 "00011" – access FIFO 8 "00100" – access Command Interface "01---" – (read) status of CY7C68001 device and addressed FIFO buffer "11---" – (write) issue a packet end for the addressed FIFO buffer (flush the buffer) "01111" – (write) reset external CY7C68001 device Also determines access to internal timing-related registers within the WB_USB itself: "10000" – access RESET_CYC register "10001" – access STROBELOW_CYC register "10010" – access STROBEHIGH_CYC register "10011" – access WRHIGH_CYC register "10100" – access ADDRSETUP_CYC register "10101" – access READSTATUS_CYC register
DAT_O	O	16	Data to be sent to host processor
DAT_I	I	16	Data received from host processor
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
INT_O	O	2/High	Interrupt output lines. Two interrupts are sent to the connected processor on this 2-bit bus: bit 0 – goes High if an interrupt is received from the CY7C68001 device (USB_INT_N is Low) and the USB_READY input is High. bit 1 – goes High if an interrupt is received from the CY7C68001 device (USB_INT_N is Low) and the USB_READY input is Low.
Interface Signals to CY7C68001 Device
USB_FIFOADR0	O	High	FIFO Address Select 0. Used in the selection of the CY7C68001 device's data FIFOs. This output pin follows bit 0 of the ADR_I input.
USB_FIFOADR1	O	High	FIFO Address Select 1. Used in the selection of the CY7C68001 device's data FIFOs. This output pin follows bit 1 of the ADR_I input.
USB_FIFOADR2	O	High	FIFO Address Select 2. Used in the selection of the CY7C68001 device's data FIFOs. This output pin follows bit 2 of the ADR_I input.
USB_D	I/O	8/16 (see note 1)	Data Bus. This is the main data bus over which internal registers and FIFO buffers of the CY7C68001 device are written and read. The CY7C68001 can provide an 8- or 16-bit data interface. The width for the data bus connecting to this interface can be defined using the associated Configure dialog for the WB_USB. Commands to internal registers are written on the USB_D[7..0] lines only. The bus defaults to a high impedance state when no data is being read or written.
USB_FLAGA (see note 2)	I	High	Flag A. Status flag for the FIFO selected using USB_FIFOADR[2..0] lines. Defaults to report the status of the FIFO's programmable flag (PF).
USB_FLAGB (see note 2)	I	High	Flag B. Status flag for the FIFO selected using USB_FIFOADR[2..0] lines. Defaults to report the status of the FIFO's full flag (FULL).
USB_FLAGC (see note 2)	I	High	Flag C. Status flag for the FIFO selected using USB_FIFOADR[2..0] lines. Defaults to report the status of the FIFO's empty flag (EMPTY).
USB_FLAGD_CS_N (see note 2)	I/O	Low	Flag D (input) / Chip Select (output). This line is used as the master chip select input line to the CY7C68001 device. This line will be taken Low when performing a read or write on the USB_D bus.
USB_RD_N	O	Low (see note 3)	Read Strobe. Take this signal Low in order to read data from the selected FIFO buffer in the CY7C68001 device. (Note: This signal connects to the SLRD pin of the CY7C68001 device)
USB_WR_N	O	Low (see note 3)	Write Strobe. Take this signal Low in order to write data to the selected FIFO buffer in the CY7C68001 device. (Note: This signal connects to the SLWR pin of the CY7C68001 device)
USB_SLOE	O	Low (see note 3)	Slave Output Enable. Used to enable reading from the selected FIFO buffer. This signal is taken Low when performing a Wishbone Read cycle.
USB_RESET_N	O	Low	Reset. This line is used to reset the CY7C68001 device. The line will be taken Low, and a reset issued, when a Wishbone Write cycle is initiated, and the ADR_I line is set to "01111".
USB_PKTEND	O	Low (see note 3)	Packet End strobe. Take this signal Low in order to commit the current buffer being written to, to the USB bus.
USB_IFCLK	O	Rise/Fall	Interface Clock. This pin is internally tied to '0'.
USB_VBUS	I	-	USB Voltage Bus.
USB_INT_N	I	Low	Interrupt. This line will be taken Low when the CY7C68001 device encounters an interrupt condition.
USB_READY	I	High	Ready. Used to gate external command reads and writes.

Notes

If interfacing to the CY7C68001 device on the peripheral board PB03, the data bus must be set to a width of 8 bits.
Assumes that the FLAGSAB and FLAGSCD registers in the CY7C680001 device have the default 00h values.
Assumes the default polarities are used for these signals.