WB_USB - Operational Overview

With respect to the WB_USB Controller itself, provided you have configured the width of the USB_D line as required, you really only need to load values for the various cycle times, after an external reset, in accordance with design requirements. If the default timings are adequate, then the Controller is ready to use straight away.

The CY7C68001 device will, however, need to be initialized after a reset.

The following sections provide an overview of initializing and communicating with the CY7C68001 device. For more detailed information on internal registers, communications and interrupt conditions, refer to the datasheet (CY7C68001.pdf) available at www.cypress.com.

Initialization

After a specific reset of the CY7C68001 device has been issued (by initiating a write with ADR_I = "01111"), you will need to initialize the CY7C68001 device. This should be carried out in accordance with design requirements and can include:

• If USB_D is configured for 8-bit data, then the CY7C68001 device's data interface must also be configured as 8-bit. By default it is 16-bit. This requires writing to the following internal registers with the value EFh:
   
  • EP2PKTLENH (at address 0Ah)
  • EP4PKTLENH (at address 0Ch)
  • EP6PKTLENH (at address 0Eh)
  • EP8PKTLENH (at address 10h).

This results in the WORDWIDE bit for each register being cleared to '0' and therefore configuring the data interface for each to 8 bit width.

• Load the required descriptor into the CY7C68001 device's 500 byte descriptor RAM. This involves writing to the DESC register (at address 30h) with:
   
  • 2 bytes defining the length of the descriptor that will be transferred, with least significant byte sent first, followed by
  • all bytes of the descriptor itself.

Accessing Internal Registers in the Cypress Device

Communication with internal registers in the CY7C68001 device is carried out through the device's Command Interface. This interface is accessed by writing or reading with the address "00100" supplied on the WB_USB's ADR_I input. The Command Interface is connected to lines 7..0 of the USB_D bus.

Writing to a Register

Writing to an internal register involves sending an 'address' byte, followed by two or more 'data' bytes. The address byte when writing a register is comprised of the following bits:

• bit 7 – '1' (specifies this is an address byte)

• bit 6 – '0' (specifies that this is a write request)

• bits 5..0 – the actual address of the register.

So to write to the EP2PKTLENH register, with address 0Ah, the address byte sent to the CY7C68001 device would be 10001010.

The two data bytes are used to send a single byte of actual data – the first byte containing the top nibble of the actual data and the second containing the lower nibble. Each byte is comprised of the following bits:

• bit 7 – '0' (specifies this is a data byte)

• bits 6..4 – don't care

• bits 3..0 – nibble of data byte being sent.

Taking the EP2PKTLENH register as example, where EFh (11101111b) is written to configure the interface as 8-bit, the two data bytes that would be sent to the CY7C68001 device would be:

• 0xxx1110 – first byte containing upper nibble of the data

• 0xxx1111 – second byte containing lower nibble of the data.

Reading from a Register

Reading from an internal register involves sending an 'address' byte, and then waiting for the CY7C68001 device to make that data available on the USB_D bus and send an interrupt to the WB_USB on the USB_INT_N line.

The address byte when reading a register is comprised of the following bits:

• bit 7 – '1' (specifies this is an address byte)

• bit 6 – '1' (specifies that this is a read request)

• bits 5..0 – the actual address of the register.

So to read the EP2PKTLENH register, with address 0Ah, the address byte sent to the CY7C68001 device would be 11001010.

Accessing FIFO Data Buffers in the Cypress Device

FIFO data buffers in the CY7C68001 device are accessed by writing or reading with the relevant address supplied on the WB_USB's ADR_I input. The address line determines which FIFO is connected to the USB_D bus as follows:

• "00000" = access to FIFO 2

• "00001" = access to FIFO 4

• "00010" = access to FIFO 6

• "00011" = access to FIFO 8

The value read from a FIFO buffer (or internal register) of the CY7C68001 device will depend on the configured width for the USB_D bus:

• 8-bit: DAT_O = "00000000" & USB_D

• 16-bit: DAT_O = USB_D

Interrogating FIFO Status

The host processor is able to read three status flags associated with the currently addressed FIFO buffer – delivered to the WB_USB at its USB_FLAGA, USB_FLAGB and USB_FLAGC inputs. In addition, the status of the CY7C68001 device itself is also read, through the USB_READY signal.

To read the status flags, bits 4..3 of the WB_USB's ADR_I input must be "01". Use bits 2..0 of the address to specify which FIFO buffer you wish to interrogate the status for:

• "01000" = interrogate status of FIFO 2

• "01001" = interrogate status of FIFO 4

• "01010" = interrogate status of FIFO 6

• "01011" = interrogate status of FIFO 8

When reading the status flags, the value appearing on the DAT_O line is comprised as follows:

DAT_O = "000000000000" & USB_READY & USB_FLAGC & USB_FLAGB & USB_FLAGA

Flushing a FIFO Buffer

A packet end can be issued for a selected FIFO buffer – committing its data to the USB bus and essentially flushing it. To perform a packet end, bits 4..3 of the WB_USB's ADR_I input must be "11". Again, use bits 2..0 of the address to specify which FIFO buffer you wish to issue the packet end:

• "11000" = send packet end for FIFO 2

• "11001" = send packet end for FIFO 4

• "11010" = send packet end for FIFO 6

• "11011" = send packet end for FIFO 8