WB_SDCARD - Host to Controller Communications

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Modified by Admin on Nov 6, 2013

Communications between a 32-bit host processor and the WB_SDCARD are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.

Table 1 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.

Table 1. Values written to internal registers during a write.

Writing to...	Results in...
DATA8	DAT_I(7..0) loaded into bits 31..24 of the TX_DATA register
DATA16	If the `endianess` bit in the Control register (CTRL.5) is '1': DAT_I(15..0) is loaded into bits 31..16 of the TX_DATA register If the `endianess` bit in the Control register (CTRL.5) is '0': DAT_I(7..0) is loaded into bits 31..24 of the TX_DATA register DAT_I(15..8) is loaded into bits 23..16 of the TX_DATA register
DATA32	If the `endianess` bit in the Control register (CTRL.5) is '1': DAT_I(31..0) is loaded into bits 31..0 of the TX_DATA register If the `endianess` bit in the Control register (CTRL.5) is '0': DAT_I(7..0) is loaded into bits 31..24 of the TX_DATA register DAT_I(15..8) is loaded into bits 23..16 of the TX_DATA register DAT_I(23..16) is loaded into bits 15..8 of the TX_DATA register DAT_I(31..24) is loaded into bits 7..0 of the TX_DATA register
CTRL	DAT_I(5..1) loaded into bits 5..1 of the Control register.
CDIV	DAT_I(15..0) loaded into bits 15..0 of the Clock Divisor register

Table 2 summarizes the 'make-up' of the 32-bit data word that is read back from each register.

Table 2. Values read from internal registers during a read.

Reading from...	Presents (to host processor)...
DATA8	"000000000000000000000000" & RX_DATA(7..0)
DATA16	If the `endianess` bit in the Control register (CTRL.5) is '1': "0000000000000000" & RX_DATA(15..0) If the `endianess` bit in the Control register (CTRL.5) is '0': "0000000000000000" & RX_DATA(7..0) & RX_DATA(15..8)
DATA32	If the `endianess` bit in the Control register (CTRL.5) is '1': 32-bit value from the RX_DATA register If the `endianess` bit in the Control register (CTRL.5) is '0': RX_DATA(7..0) & RX_DATA(15..8) & RX_DATA(23..16) & RX_DATA(31..24)
CTRL	32-bit value from the Control register
STATUS	32-bit value from the Status register
CDIV	32-bit value from the Clock Divisor register
CARD_DET	32-bit value from the Card Detection register