WB_PWMX - Block Diagram

Figure 1 shows a high-level block diagram for the WB_PWMX component.

Figure 1. WB_PWMX block diagram.

The core is fully synchronous, with both counters and the comparator clocked using the external system clock signal (CLK_I).

The resolution of the PWM Counter and PWM Comparator modules depends on the resolution mode specified for the Controller using the mod1 and mod0 bits of the PWCON register. Table 1 shows the reload values for the PWM Counter – the value loaded after a reset of the Controller or upon counting past zero.

After a reset, the PWM Counter is set to its maximum value, in accordance with the current resolution mode. The 16-bit Pre-scaler Counter is used to provide an enable line to the PWM Counter. The Pre-scaler Counter is decremented on each rising edge of the CLK_I signal. When it counts past zero, the enable signal is taken high and the PWM Counter is decremented.

The value of the PWM Counter is then compared against the specified pulse width in the 14-bit PWMRG register and the complimentary outputs – PWMP and PWMN – generated accordingly.

When the Pre-scaler Counter reaches zero, it is automatically reloaded with the 16-bit value stored in the PWPHI and PWPLO registers.

An interrupt will be generated when either of the two counters overflow (count past zero).

For information on the internal registers for the WB_PWMX that can be accessed from the host processor, see Accessible Internal Registers.