WB_MP3DEC - Accessible Internal Registers
Contents
- Status and Control Register (STATUS)
- Interrupt Mask Register (INTMASK)
- Read Start Address Register (READADDRESS)
- Read End Address Register (READENDADDRESS)
- Write Address Register (WRITEADDRESS)
- Scratch Address Register (SCRATCHADDRESS)
- Header Register (HEADER)
- Core Version and Endianness Register (VERSION)
The following sections detail the internal registers for the WB_MP3DEC that can be accessed from the host processor.
Status and Control Register (STATUS)
Address: 0h
Access: Read/Write
Size: 5 bits
Reset value: 3
Bit | Access | Name | Function |
|---|---|---|---|
0 | Write | Start | Write '1' to start decoding |
1 | Read/Write | Reset | Reading '1' indicates the core is idle |
2 | Read/Write | ReadEmpty | Reading '1' indicates no more input to read |
3 | Read/Write | WriteReady | Reading '1' indicates a frame has been written |
4 | Read/Write | HeaderReady | Reading '1' indicates a new header is available |
All unused bits return '0' when read. They are ignored when written.
Interrupt Mask Register (INTMASK)
Address: 1h
Access: Read/Write
Size: 5 bits
Reset value: 0
Is AND-ed with the STATUS register, if non zero the interrupt line is made active. The value read is the value written by the user with the unused bits set to '0'.
Read Start Address Register (READADDRESS)
Address: 2h
Access: Read/Write
Size: 30 bits
Reset value: 0
This is the address of the input data which the core will read over its data memory wishbone bus. Reading will continue until READADDRESS matches READENDADDRESS, upon which the decoder will stop reading and the STATUS.ReadEmpty bit will be set.
Writing to this register will set the STATUS.ReadEmpty bit, allowing READENDADDRESS to be set as well before the core will continue. Actual reading only starts after the STATUS.ReadEmpty bit has been cleared by writing '1' to it, or by starting a fresh decode by writing '1' to STATUS.Start.
The value read is the address of the next word to be read by the core. Bits 0 and 1 are always '00'.
Read End Address Register (READENDADDRESS)
Address: 3h
Access: Read/Write
Size: 30 bits
Reset value: 0
See READADDRESS for usage.
Writing to this register will set the STATUS.ReadEmpty bit, allowing READADDRESS to be set as well before the core will continue. Actual reading only starts after the STATUS.ReadEmpty bit has been cleared by writing '1' to it, or by starting a fresh decode by writing '1' to STATUS.Start.
The value read is the value written by the user with bits 0 and 1 set to '00'.
Write Address Register (WRITEADDRESS)
Address: 4h
Access: Read/Write
Size: 30 bits
Reset value: 0
This is the start address of the output area which the core will write over its data memory wishbone bus. The size of the area is 576 32-bit words (576x2 signed 16-bit stereo samples). Decoded samples will be written starting at WRITEADDRESS until 576 stereo samples have been written, upon which the STATUS.WriteReady bit will be set.
The value read is the value written by the user with bits 0 and 1 set to '00'.
Scratch Address Register (SCRATCHADDRESS)
Address: 5h
Access: Read/Write
Size: 30 bits
Reset value: 0
This is the start address of the scratch area which the core will read and write over its scratch memory wishbone bus. The size of the area is 6080 32-bit words.
The value read is the value written by the user with bits 0 and 1 set to '00'.
Header Register (HEADER)
Address: 6h
Access: Read
Size: 32 bits
Reset value: unknown
Whenever the core recognizes an MP3 header word in its input, the STATUS.HeaderReady bit will be set and the header word will be copied to this register.
Note that the decoder does not wait in any way, the only guarantee is that the following logic will always process unique headers (but not necessary all headers will be seen):
- Write '1' to STATUS.HeaderReady
- Wait for STATUS.HeaderReady to become '1'
- Read HEADER with an atomic read
- Repeat from step 1
Note that the core always produces two-channel output. It is up to the user to read the bits from the MP3 header word (copied into the Header register) if the difference between a duplicate-mono, stereo, or dual-track must be known.
Core Version and Endianness Register (VERSION)
Address: Fh
Access: Read/Write
Size: 9 bits
Reset value: 10h
Bit | Access | Name | Function |
|---|---|---|---|
0..7 | Read | Version | Core version (10h = version 1.0) |
8 | Read/Write | LittleEndian | If '1' the core is in little-endian mode, if '0' in big-endian mode |
All unused bits return '0' when read. They are ignored when written.