WB_MEM_CTRL Configuration - Synchronous DRAM Settings

When the chosen memory type is Synchronous DRAM, the Configure (Memory Controller) dialog will appear as shown in Figure 1.

Figure 1. Configuration options when interfacing to SDRAM.

The following sections detail each of the configuration options available.

Size of SDRAM Memory

Use this region to specify the size of the physical SDRAM that you are interfacing to. The width of the ADR_I input line will automatically change in accordance with the memory size specified.

Table 1 lists the supported SDRAM sizes and the corresponding size of the Wishbone address bus (ADR_I) for each configuration of the Memory Controller.

X – Memory Layout not available for chosen SDRAM size.

Memory Layout

Use the drop-down in this region of the dialog to select the layout for the physical memory. The following is a list of all possible layouts:

• 1 x 32-bit Wide Device

• 1 x 16-bit Wide Device

• 1 x 8-bit Wide Device

• 2 x 16-bit Wide Devices

• 2 x 8-bit Wide Devices.

The actual layouts available will depend on the chosen size of SDRAM memory. Refer back to Table 1 to see which layouts are available with which memory sizes.

The schematic symbol for the placed Memory Controller will automatically be updated to reflect your selection, upon leaving the dialog.

In addition to determining the interface pinout for connection to the physical memory device(s), the memory layout also determines the number of accesses required to read or write a single 32-bit word.

Memory Settings

Use this region of the dialog to specify the speed of the memory you are working with (in MHz). The frequency of the signal arriving at the Controller's SDRAM_CLK input must equal the value specified for the SDRAM Clock Frequency in MHz.

The Keep Current Row Open option allows you to keep the current row open – essentially disabling the SDRAM device's auto-precharge feature, which otherwise causes a precharge of the addressed bank/row upon completion of the current Read or Write. This enables faster memory access when successively accessing the same row. If this option is set to No, the SDRAM device's auto-precharge feature is enabled and the current row will be closed after each memory access.

Both settings in this region are used to calculate reload values for refresh counters internal to the Controller.

Timer Settings

The following timing-related settings can be defined in this region of the dialog, with each setting specified in terms of cycles of the SDRAM_CLK signal. Together, these settings are used to determine memory timing protocols.

• Write Recovery time (tWR) – the minimum number of clock cycles between registration of the last required data element in a Write access and the start of a subsequent precharge for that row/bank. (Default = 4 cycles).

• Auto Refresh period (tRFC) – the number of clock cycles required for the SDRAM device to perform one Auto Refresh cycle. (Default = 16 cycles).

• Active to Read or Write delay (tRCD) – the minimum number of clock cycles that must be observed between the start of an access to memory (a particular row of a bank is opened for access) and the Read or Write actually being performed. (Default = 8 cycles).

• Precharge command period (tRP) – the number of clock cycles required to perform a precharge, which is simply the closing of the open row in a specific bank or the open row in all banks. During a precharge, the bank(s) will be idle and no Read or Write access is permitted. (Default = 16 cycles).

• CAS latency (tCAS) – the delay, in clock cycles, between the SDRAM device registering a Read access and the availability of the first piece of output data. This is typically set to 2 or 3 clock cycles (Default = 2 cycles).

The drop-down field at the bottom of this region allows you to define the synchronization scheme to be used when interfacing to SDRAM. The following three options allow you to specify the relationship between the SDRAM_CLK input – the frequency of which is the same as the speed of memory you are using – and the external system clock, CLK_I – input to the processor and used as the Wishbone clock.

• Independent Clocks – use this option when the memory is being clocked at a higher speed than the FPGA design. This option provides flexibility when debugging a design, as you can use any frequency for CLK_I (provided it's lower than SDRAM_CLK). However time is lost, in terms of data throughput, performing a resync between the Wishbone interface and the memory controller.

• Memory Clock 2x Wishbone Clock – use this option when the memory is being clocked at twice the speed of the FPGA design (e.g. SDRAM running at 100MHz and system clock for the design (CLK_I) is 50MHz). Time is still lost when performing a resync, but the resync is preformed faster due to prior knowledge of the relationship between the clocks. You can slow down the design clock, but this will result in the memory becoming slower too.

• Same Clock – use this option when the memory is being clocked at the same speed as the FPGA design. This option is typically for slower FPGA devices, which can not be clocked as high as 100MHz. No resync is required between the Wishbone interface and the memory controller.