WB_IRRC - Interrupts

The WB_IRRC generates a single interrupt flag – rxint – which is reflected in bit 0 of the Status register. The source of the interrupt depends on the current operational mode set for the peripheral:

• NEC Encoder/Decoder mode (CTRL[7..6] = "01") – the level of rxint follows the level of internal interrupt signal nec_rxint, which is generated within the NEC Decoder Unit. The nec_rxint signal goes High if valid command data is received.

• RC5 Decoder mode (CTRL[7..6] = "10") – the level of rxint follows the level of internal interrupt signal rc5_rxint, which is generated within the RC5 Decoder Unit. The rc5_rxint signal goes High if valid command data is received.

• RAW Interface mode (CTRL[7..6] = "00") – the level of rxint follows the level of internal interrupt signal raw_rxint, which is generated within the RAW Decoder Unit. The raw_rxint signal goes High if an edge is detected on the demodulated signal.

The interrupt can be exported to the processor on the INT_O line, provided the inten bit in the Control register (CTRL.0) is set.

The rxint flag (and its associated internal source interrupt signal) is cleared by writing a '1' to the rxintrst bit of the Control register (CTRL.1).

Figure 1 summarizes the mechanics of interrupt generation for the WB_IRRC.

Figure 1. Interrupt generation for the WB_IRRC.