WB_INTERFACE - Pin Description
Frozen Content
The following pin description is for the WB_INTERFACE component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interface. The component's external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
The pin description includes examples of each supported interface item and the pins involved (both Read & Write where applicable). The actual pins in the interface will vary, depending on the number and type of items added, and how those items have been configured.
| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock signal |
| RST_I | I | High | External (system) reset |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| ACK_O | O | High | Standard Wishbone acknowledgement signal. When this signal goes high, the WB_INTERFACE (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 0-32 (see note 1) | Standard Wishbone address bus, used to address the items of the customized interface. Internal registers and command sets each occupy a single address. External address ranges occupy an address range corresponding to their configured address bus widths. |
| DAT_O | O | 8/16/32 (see note 2) | Data to be sent to host processor |
| DAT_I | I | 8/16/32 (see note 2) | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| Custom Interface Signals (Example Items) | |||
| Whole Internal Register (IR) | |||
| IRName_I | I | 1-32 (see note 3) | Data input from connected logic |
| IRName_O | O | 1-32 (see note 3) | Data output to connected logic |
| Sliced Internal Register (IR) - 2 slices shown | |||
| IRName_Slice1Name_I | I | Range1 (see note 4) | Slice 1 data input from connected logic. The Range1 bits of data will be loaded into the relevant bits of internal register IRName, as defined by register slice Slice1Name. |
| IRName_Slice1Name_O | O | Range1 (see note 4) | Slice 1 data output to connected logic. The Range1 bits of data in internal register IRName, as defined by register slice Slice1Name, will be sent to the connected logic. |
| IRName_Slice2Name_I | I | Range2 (see note 4) | Slice 2 data input from connected logic. The Range2 bits of data will be loaded into the relevant bits of internal register IRName, as defined by register slice Slice2Name. |
| IRName_Slice2Name_O | O | Range2 (see note 4) | Slice 2 data output to connected logic. The Range2 bits of data in internal register IRName, as defined by register slice Slice2Name, will be sent to the connected logic. |
| Command Set (CS) - Single command class configured with 2 commands and 2 operands | |||
| CSName_CmdClassName_Cmd1Name_O | O | High | Output pin for command Cmd1Name, which is part of the command class CmdClassName, within the defined command set CSName. |
| CSName_CmdClassName_Cmd2Name_O | O | High | Output pin for command Cmd2Name, which is part of the command class CmdClassName, within the defined command set CSName. |
| CSName_CmdClassName_Op1Name_O | O | Range1 (see note 5) | Output pin for command operand Op1Name, which is part of the command class CmdClassName, within the defined command set CSName. This operand output will be used by all commands defined within the same parent command class. |
| CSName_CmdClassName_Op2Name_O | O | Range2 (see note 5) | Output pin for command operand Op2Name, which is part of the command class CmdClassName, within the defined command set CSName. This operand output will be used by all commands defined within the same parent command class. |
| CSName_ACK_I | I | High | Acknowledge signal. This pin will be present if, when defining the command set, the Immediate Acknowledgement option is left disabled. The connected logic must take this pin High to generate the acknowledge signal (High) on the WB_INTERFACE'S ACK_O line to the host processor. |
| External Address Range (EAR) | |||
| EARName_ADR_O | O | 0-32 (see note 6) | Address bus. |
| EARName_DAT_I | I | 1-32 | Data input from connected logic. |
| EARName_DAT_O | O | 1-32 | Data output to connected logic. |
| EARName_RD_O | O | High | Read enable for the connected logic. |
| EARName_WR_O | O | High | Write enable for the connected logic. |
| EARName_ACK_I | I | High | Acknowledge signal. This pin will be present if, when defining the external address range, the Immediate Acknowledgement option is left disabled. The connected logic must take this pin High to generate the acknowledge signal (High) on the WB_INTERFACE'S ACK_O line to the host processor. |
Notes
- Automatically determined based on the items defined for the interface.
- The width of the data bus for the Wishbone interface to the host processor is specified as part of the component's configuration. It must be greater than, or equal to, the largest data width specified for items in the interface.
- The width of the data bus for an internal register is defined as part of its configuration. It must be less than, or equal to, the width specified for the Wishbone data bus of the WB_INTERFACE component.
- Each slice must be a contiguous group of bits and no slices can overlap. For the single register IRName, the bit ranges defined for each of the constituent slices (e.g. Range1, Range2,...,Range N ) can not exceed the defined data width for the register.
- The bit ranges of operands in the same command class must comprise of contiguous bits and can not overlap. The usable operand bit ranges in a particular command class will be dependent on the data width specified for the command set and how many commands are defined in that set.
- The width of the address bus for the external address range is defined as part of its configuration. If only one address is defined (0 bits) there will be no EARName _ADR_O pin. The maximum width of the address will depend on the number of items defined in the custom interface.