WB_INTERFACE - Concepts

The FPGA-ready Wishbone-compliant components supplied with Altium Designer can be thought of as an extensive set of building blocks. For many 32-bit processor-based designs, these will be sufficient for the design task. However, you may need to implement other pieces of hardware that don't exist among these pre-packaged blocks. This can be achieved, for example, by using generic logic components on a sub-sheet, or a referenced C or HDL (VHDL/Verilog) file. The role of the Custom Wishbone Interface component is to provide the means by which to hook that hardware into your existing Wishbone system – so that it can be 'seen' and communicated with, by a processor therein.

The Custom Wishbone Interface component achieves this by enabling you to build your own customized Wishbone peripheral, without having to learn any of the intricacies of the Wishbone bus itself. Figure 1 illustrates the concept of the Custom Wishbone Peripheral in a design.

Figure 1. The Custom Wishbone Peripheral concept.

The interface to your custom logic is fully customizable – you tailor it to meet the needs of your custom logic, for example to interrogate some registers, or issue commands to make something in your logic happen. The advantage of this is that you are not constrained to build logic that has to connect to a rigidly defined interface. You build your logic and then tailor the interface to suit your needs.

The interface to your main processor system is simply a standard Wishbone interface. Connect directly to an Interconnect component in your system. The width of the Address bus is handled automatically for you, depending on the configuration of any external address range items in your customized interface. All you need to do is set a width for the Data bus!

Example Usage

The best way to illustrate the concept of a customizable Wishbone interface component, and how it can be used to enhance and extend your FPGA designs, is to look at an example. Consider the custom logic component in Figure 2, which represents a set of 16 banks of registers. Each register bank comprises 32 x 32-bit registers. Such a component might be used in a CPU as shadow registers, to optimize context switching.

Figure 2. Example custom logic component (high-level illustration).

Considering the operation of this component and how each of its pins are used:

• Only one register bank can be active at a time. The currently active register bank is indicated by the value at the CUR_REG_BANK_O output. The active bank can be changed by driving the CHANGE_REG_BANK_I signal High and specifying the required bank at the BANK_NUM_I input. The component's ACK_O signal is driven High to indicate the successful switching of register banks.

• The value of a register in the currently active bank can be written by:
   
  • Driving the REG_WR_I pin High
  • Specifying the required register using the REG_ADR_I input
  • Specifying the value to be written to this register at the REG_DAT_I input
     
• The value of a register in the currently active bank can be read by:
   
  • Driving the REG_RD_I pin High
  • Specifying the required register using the REG_ADR_I input
  • Reading the value made available at the REG_DAT_O output.

This is quite a handy little piece of hardware – custom logic that is not available as a pre-packaged component delivered with the software. Suppose now that we wish to interact with this component from a 32-bit Wishbone-compliant processor in an FPGA design. The component itself is not Wishbone-compliant. It is possible however, to build a custom Wishbone peripheral without the need to know any details of the Wishbone bus – and that's where the Custom Wishbone Interface component (WB_INTERFACE) comes in.

As a quick reminder, the WB_INTERFACE component has a Wishbone bus and a fully customizable interface for transferring data to/from connected logic. The individual units of this configurable interface are referred to as 'items'. The interface can include a combination of one or more of the following items:

• Internal Registers – which allow values to be read from, and/or written to, connected logic.

• Command Sets – which allow operations to be enabled on connected logic.

• External Address Ranges – which allow access to blocks of addresses on connected logic.

For our example custom logic device, the Custom Wishbone Interface component can be used as outlined in Figure 3. Note that the custom logic device (not shown) is defined in a sub-sheet, referenced by a sheet symbol on the top-level schematic.

Figure 3. Configure the Wishbone Interface to communicate with your custom logic as required and extend the
capabilities of your design.

The interface to the custom logic device is configured to have the following three items:

• CUR_REG_BANK (Internal Register item) – this item is configured as a read register for reading the value of the currently active register bank.

• CHANGE (Command Set item) – this item is configured with a command, BANK, which tells the custom component to switch register banks. It has an associated operand, BANK_NUM, which is the desired register bank to switch to.

• REG (External Address Range item) – this item is configured to handle the reading and writing of values to the desired registers in the currently active register bank. The index of the desired register is output on the item's REG_ADR_O line. Data is transferred to/from the custom logic component using the item's REG_DAT_O and REG_DAT_I lines.