WB_I2S - Pin Description
The following pin description is for the WB_I2S when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_I2S pin description.| Name | Type | Polarity / Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock signal |
| RST_I | I | High | External (system) reset |
| CLK_BASE | I | Rise | Base Clock. This signal is used in the generation of the three clock signals from the device:
This clock is also used by the Transmit and Receive sections of the device. This signal is independent of the CLK_I signal, which is used to clock transfers over the Wishbone interface. For normal operations however, the base clock input can be wired to the board clock signal (CLK_I). |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_I2S (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 2/3 (see note 1) | Address bus, used to select an internal register of the device for writing to/reading from |
| DAT_O | O | 32 | Data to be sent to host processor |
| DAT_I | I | 32 | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| INT_O | O | High | Interrupt output line. An interrupt can be generated based on the comparison of the level of data in the Receive or Transmit FIFOs, with the value defined for the watermark, loaded into the Control register. See Interrupt Generation. |
| I2S Bus Interface Signals | |||
| SCK | O | Rise | Continuous serial clock (bit clock). The frequency of this signal is calculated as 64 * fWS, where fWS is the frequency of the Word Select line and is equal to the sample rate. |
| WS | O | Level | Word Select. For standard I2S communication (non-justified): 0 = Left Channel For communication in left/right justified modes: 0 = Right Channel This signal not only determines the data channel, but also is used to effectively delimit transmitted data words. WS always changes state one clock cycle (SCK) before the MSB of the next data word is transmitted. The frequency of WS is equal to the sample rate. In one cycle of WS, one sample (left + right channel, or right + left channel) can be transmitted. |
| SDO | O | 1 | Serial Data Out |
| SDI | I | 1 | Serial Data In |
| ADCK | O | Rise | Additional Serial Clock. The frequency of this signal is calculated as 256 * fWS, where fWS is the frequency of the Word Select line and is equal to the sample rate. This signal is typically wired to the MCLK input of an external audio CODEC device. |
Notes
- If the WB_I2S is configured to use a HW buffer, the address line will be 3 bits. If the HW buffer is disabled, the address line will be 2 bits.