WB_BOOTLOADER_V2 - Pin Description
The following pin description is for the WB_BOOTLOADER_V2 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to the SPI bus will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_BOOTLOADER_V2 pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK | I | Rise | External (system) clock signal |
| RST | I | High | External (system) reset |
| ENABLE | I | High | Enable signal. Typically tie this input High (to VCC) to enable bootloading functionality |
| CPU_HOLD | O | High | CPU Hold signal. This signal should be connected to the processor's RST_I input and provides a separate reset signal to the processor and its connected I/O peripheral devices. All memory devices in the system are still reset using the standard RST signal. This signal ensures that the processor and its I/O slaves are not reset until after the WB_BOOTLOADER_V2 has finished copying from the serial Flash memory to the SRAM. This signal will be taken High if the bootloading process is not yet finished, OR if an external reset is received on the component's RST input. |
| Host Processor Interface Signals | |||
| io_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| io_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| io_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_BOOTLOADER_V2 (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| io_ADR_I | I | 3 | Address bus, used to select an internal register of the device for writing to/reading from |
| io_DAT_O | O | 32 | Data to be sent to host processor |
| io_DAT_I | I | 32 | Data received from host processor |
| io_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| io_CLK_I | I | Rise | External (system) clock signal. This signal is identical to the CLK_I input of the processor, and is simply the clock line output as part of the processor's External Peripheral I/O interface. |
| io_RST_I | I | High | External reset signal. This signal is identical to the RST_I input of the processor, and is simply the reset line output as part of the processor's External Peripheral I/O interface. |
| io_INT_O | O | High | Interrupt output line. This signal is currently not supported and is grounded internally |
| SRAM Interface Signals | |||
| me_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| me_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| me_ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the connected Wishbone memory device has finished execution of the requested action and the current bus cycle is terminated |
| me_ADR_O | O | 20 | Standard Wishbone address bus, used to select an address of the connected Wishbone memory for writing to/reading from |
| me_DAT_I | I | 32 | Data received from external Wishbone memory |
| me_DAT_O | O | 32 | Data to be sent to external Wishbone memory |
| me_SEL_O | O | 4/High | Select output, used to determine where data is placed on the me_DAT_O line during a Write cycle, and from where on the me_DAT_I line data is accessed during a Read cycle. For the WB_BOOTLOADER_V2, only 32-bit data transfers to/from Wishbone memory are supported, meaning that all the lines go High during a Write or Read cycle |
| me_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| me_CLK_O | O | Rise | External (system) clock signal (identical to CLK), made available for connecting to the CLK_I input of a slave memory device. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| me_RST_O | O | High | Reset signal made available for connection to the RST_I input of a slave memory device. This signal goes High when an external reset is issued to the WB_BOOTLOADER_V2 on its RST pin. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| SPI Bus Interface Signals | |||
| SPI_DOUT | O | - | Serial Data Out. This data is sent from the host processor to the target SPI device resource. |
| SPI_DIN | I | - | Serial Data In. This is data received from the target SPI device resource, to be sent to the host processor. |
| SPI_CLK | O | - | Serial Clock. This signal is generated by the WB_BOOTLOADER_V2 and is used to clock data in and out during communication with the target SPI device resource. |
| SPI_MODE | O | Level | Serial Mode. When using the WB_BOOTLOADER_V2 as a standard SPI Controller, this signal is used to switch between the following two modes of access: 0 = Communicate directly with a slave device over the SPI bus 1 = Communicate with the NanoBoard's SPI Controller, resident within the NanoTalk Controller FPGA. More specifically, access is made to an 8-bit SPI device address register therein, which is used to store the address of the required SPI slave device you wish to communicate with. Writing to this register is the only means by which the design may be granted access to the SPI bus. The level of this signal is controlled directly by the mode bit in the Control register (CTRL.2). |
| SPI_CS | O | Level | Serial Chip Select. When using the WB_BOOTLOADER_V2 as a standard SPI Controller, take this signal Low to enable communications with the target SPI device, once the address for that device has been sent to the NanoBoard's SPI Controller, access to the SPI Bus has been granted, and the mode of access has been switched to direct communications (SPI_MODE taken Low). The level of this signal is controlled directly by the cs bit in the Control register (CTRL.1). |
For detailed information on the SPI communications systems in place on the NanoBoard NB2 and NanoBoard 3000, and how the SPI_MODE and SPI_CS lines are used, see SPI Communications on the Desktop NanoBoard NB2DSK01 and SPI Communications on the NanoBoard 3000, respectively.