VGA32_TFT Controller - Pin Description
Frozen Content
The following pin description is for the VGA32_TFT Controller (configured WB_VGA component) when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_VGA Pin description (configured as VGA32_TFT Controller).| Name | Type | Polarity / Bus size | Description |
|---|---|---|---|
| Global Control Signals | |||
| io_CLK_I | I | Rise | Global Wishbone clock input. This clock is used to drive both Master and Slave interfaces |
| io_RST_I | I | High | Global Wishbone reset |
| Host Processor Interface Signals | |||
| io_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| io_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| io_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| io_ADR_I | I | 12 | Address bus, used to select an internal register of the device for writing to/reading from |
| io_DAT_O | O | 32 | Data to be sent to host processor |
| io_DAT_I | I | 32 | Data received from host processor |
| io_SEL_I | I | 4/High | Select input, used to determine where data is placed on the io_DAT_O line during a Read cycle and from where on the io_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| io_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| io_INT_O | O | 3/High | Interrupt output lines. Three interrupts are sent to the connected processor on this 3-bit bus. bit 0 = VSYNC |
| Video Memory Interface Signals | |||
| me_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| me_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| me_ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes High, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated |
| me_ADR_O | O | 32 | Standard Wishbone address bus. Used to select an address in the connected Wishbone slave device for writing to/reading from |
| me_DAT_I | I | 32 | Data received from the connected Wishbone slave device |
| me_SEL_O | O | 4/High | Select output, used to determine where data is placed on the me_DAT_O line during a Write cycle and from where on the me_DAT_I line data is accessed during a Read cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| me_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read Note: This signal is always Low as the Controller does not write to Video memory, it only reads data from memory. |
| TFT Panel Interface Signals | |||
| TFT_RED | O | 5 | Provides the 5-bit digital signal for the intensity of red used in composing a pixel's displayed color |
| TFT_GREEN | O | 6 | Provides the 6-bit digital signal for the intensity of green used in composing a pixel's displayed color |
| TFT_BLUE | O | 5 | Provides the 5-bit digital signal for the intensity of blue used in composing a pixel's displayed color |
| TFT_CL | O | 3/High | This bus consists of the following three lines: TFT_CL(3) = Gate Driver Shift Clock |
| TFT_DISP_ON | O | Low | Sets all outputs to VGL – the negative power supply for the TFT panel's Gate Driver |
| TFT_M | O | High | AC Modulation Clock |
| TFT_POL | O | Low | Data Polarity Judge Pulse |
| TFT_STH | O | High | Source Driver Start Pulse |
| TFT_STV | O | Low | Gate Driver Start Pulse |