TMR3_W - Pin Description

Frozen Content

Modified by Admin on Nov 6, 2013

The following pin description is for the TMR3_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. TMR3_W Pin description.

Name	Type	Polarity/Bus size	Description
Control Signals
CLK_I	I	Rise	External system clock
RST_I	I	High	External system reset
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle.
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone-device acknowledgement signal. When this signal goes high, the Timer Unit (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated.
ADR_I	I	3	Standard Wishbone address bus, used to select an internal register of the Wishbone slave device for writing to/reading from.
DAT_O	O	8	Data to be sent to an external Wishbone master device (i.e. host processor).
DAT_I	I	8	Data received from an external Wishbone master device (i.e. host processor).
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read 1 = Write
INT_O	O	High	Interrupt signal. If either Timer A or Timer B have reached overflow state (i.e. either of the corresponding overflow bits in the Timer Control register are set), this signal is activated. This alerts the host processor to the fact that the timer/counter has reached its upper limit and has rolled over to start counting from zero.
Timer Input Signals
TA	I	Rise	Timer A external clock input
GATEA	I	High	External Timer A enable input. If bit 3 of the Timer Mode register is set (1), Timer A is enabled solely by this external input.
TB	I	Rise	Timer B external clock input
GATEB	I	High	External Timer B enable input. If bit 7 of the Timer Mode register is set (1), Timer B is enabled solely by this external input.
Timer Output Signals
TB_OV	O	High	Timer B overflow output. This signal is taken high for a single period of the external system clock signal (CLK_I) when: TLB register (low byte of Timer B) reaches overflow state and current mode is mode 2. THB register (high byte of Timer B) reaches overflow state and current mode is mode 0,1 or 3.