TMR3_W - Host to Controller Communications
Communications between a 32-bit host processor and the TMR3_W are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the 8-bit data word from the host processor is used by each of the internal registers.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
TCON | DAT_I(7..4) loaded into bits 7..4 of the Timer Control register |
TMOD | DAT_I(7..0) loaded into the Timer Mode register |
TLA | If current mode is Mode 0:
DAT_I(4..0) loaded into bits 4..0 of the Timer A Low register (bits 7..5 loaded with zeroes)
If current mode is Mode 1, Mode 2, or Mode 3:
DAT_I(7..0) loaded into the Timer A Low register. |
TLB | If current mode is Mode 0:
DAT_I(4..0) loaded into bits 4..0 of the Timer B Low register (bits 7..5 loaded with zeroes)
If current mode is Mode 1, Mode 2, or Mode 3:
DAT_I(7..0) loaded into the Timer B Low register. |
THA | DAT_I(7..0) loaded into the Timer A High register |
THB | DAT_I(7..0) loaded into the Timer B High register |
Table 2 summarizes the 'make-up' of the 8-bit data word that is read back from each register.
| Reading from... | Presents (to host processor)... |
|---|---|
TCON | 8-bit value from the Timer Control register |
TMOD | 8-bit value from the Timer Mode register |
TLA | 8-bit value from the Timer A Low register |
TLB | 8-bit value from the Timer B Low register |
THA | 8-bit value from the Timer A High register |
THB | 8-bit value from the Timer B High register |