TMR3_W - Block Diagram

Figure 1 shows a high-level block diagram for the TMR3_W component.

Figure 1. TMR3_W block diagram.

The TMR3_W has two 16-bit registers: Timer A and Timer B. Both registers are further sub-divided into two 8-bit registers – TLA and TLB (low 8 bits); THA and THB (high 8 bits).

Both registers can be configured for counter or timer operations.

In timer mode, the register is incremented after every 12 cycles of the external system clock (CLK_I) signal. The required clock signal for each timer is obtained from the Internal Clock Generation Unit. This unit essentially provides a divide by 12 counter, whose input is the CLK_I signal and whose outputs are the internal clock signals TA_CLK_I and TB_CLK_I.

In counter mode, the register is incremented when a rising edge is observed at the corresponding external clock input pin (TA or TB). The maximum input count rate is 1/24 of the external clock frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least one period of the external clock signal.

For information on the internal registers for the TMR3_W that can be accessed from the host processor, see Accessible Internal Registers.