Sharing Block RAM between two Processors

Although connection to Block RAM is made simple through use of a Memory Controller configured as a BRAM Controller, access to this type of memory will be inherently slower due to its synchronous nature, and therefore the extra clock cycles involved with accessing it. However, when sharing memory between processors, true dual-port Block RAM can be used and without the need for a bus arbitration component. In fact, both processors can access the memory simultaneously, without having to wait or incur any arbitration cycles imposed by the arbiter.

Figure 1 shows an example of the wiring involved (in a schematic-based design) for two TSK3000A processors to access a 64K x 32-bit dual port Block RAM device. Note that Wishbone Interconnect components have been used for convenience in both connection and address mapping between processor (32-bit) and slave memory device (in this case 16-bit).

Figure 1. Sharing true dual-port Block RAM between processors.