PS2_W - Transmission Protocols
The PS2_W Controller implements a bidirectional protocol for synchronous serial transmission between the host and the PS/2 device (keyboard or mouse).
The PS/2 device sends information to the Controller, for example when a key is pressed on the keyboard, or when the mouse has moved position.
The Controller sends information to the PS/2 device when a specific command —- sent from the processor —- needs to be executed. When the connected PS/2 device is a keyboard, such a command could be to change the state of an LED (Num Lock, Caps Lock, Scroll Lock).
The clock signal for the Controller-Device interface (PS2CLK) is always generated by the PS/2 device, but is not continuous. Total control over transmission is, however, ultimately in the hands of the processor. The table below illustrates the various states that can be entered, with respect to the Controller-Device interface.
Table 1. PS2 Controller Transmission states.| State | PS2DATA | PS2CLK | Note |
|---|---|---|---|
| Idle | High | High | - |
| Inhibit Transmission | High | Low | Here, the Controller is asking the PS/2 device to generate the clock, in order for the transmitter to transmit serial data out of the shift register. |
| Host Send Request | Low | High |
Note that the Host Send Request state can only be entered by passing through the Inhibit Transmission state.
Transmission from PS/2 Device to Controller
The PS/2 device is free to send data to the Controller when the Controller is in the Idle state. This means that both the PS2CLK and PS2DATA lines are high. The PS/2 device must then wait for half a PS2CLK period before it can start its transmission.
The transmitted data is sent in frames, with each frame carrying a single byte of data. The number of frames sent depends on the number of bytes of data constituting the message to be sent. For example, most scan codes (the codes that represent keys) for a keyboard are a single byte in length, but some can be longer. When sending information to tell the host processor that a key has been released, an extra byte of data needs to be sent. It should be noted that only a single byte of data (therefore a single frame) can be sent to the Controller at any one time. To send additional bytes of data (further frames) the PS/2 device must wait until the Controller returns to the Idle state, before starting each additional transmission.
When sending data from the device to the Controller, the PS2 frame consists of 11 fields. The order of these fields is shown in Table 2.
Table 2. PS2 Frame (from PS/2 device to Controller).| Start | Data 0 | Data 1 | Data 2 | Data 3 | Data 4 | Data 5 | Data 6 | Data 7 | Parity | Stop |
Start | – | indicates the start of a transmitted frame. This is always a '0'. |
Data0-Data7 | – | the actual data bits. The least significant bit (Data0) is always sent first. |
Parity | – | used for error detection. Odd parity is used. Therefore, if the number of '1's in Data0-7 is even, the Parity bit is set (1). If the number of '1's is odd, the Parity bit is cleared (0). |
Stop | – | indicates the end of the frame currently being transmitted. This is always a '1'. |
Figure 1 shows the timing for this frame transmission. The PS2_W Controller reads each bit in the frame on the falling edge of the clock signal.
Figure 1. Transmission of data from PS/2 device to Controller.
The host processor, as previously mentioned, always has full control over the transmission of data to and from the PS/2 device:
- By monitoring the
busyflag in the Wishbone Control register (WCREG.0), it knows the current status of the PS2_W Controller – whether it is sending data to, or receiving data from, the connected PS/2 device
- The INT_O signal alerts it to any data that has been received by the PS2_W Controller and is therefore ready to be read.
The host can therefore complete reception of data or start a transmission, whenever it deems is appropriate to do so.
The transmission of data from the PS/2 device to the Controller can be inhibited at any time, by the host setting the stb flag in the Wishbone Control register (WCREG.1). The PS2_W Controller, detecting that the host wants to interrupt, takes the PS2CLK line low for at least one clock period.
When such an event arises, the Controller enters the Inhibit Transmission state. The response of the PS/2 device depends on where in the transmission the inhibit occurs:
- before reception of the Start bit – the PS/2 device has not yet begun transmission of the data. The frame of data will be buffered until the interface re-enters Idle state and the device is free to commence transmission.
- during transmission of a frame (anywhere after the first high-to-low transition of PS2CLK and before the last high-to-low transition) – the PS/2 device aborts transmission and prepares to retransmit the entire message again. The message could be a single byte scan code, in which case the same byte will be retransmitted when the interface re-enters Idle state. If the message being transmitted was composed of several bytes (for example an extended key on a keyboard has been pressed or released), all bytes would be retransmitted, irrespective of how many bytes of the message had already been transmitted.
- After reception of the Stop bit – the PS/2 device has finished transmission of the data (constituent frames) and so retransmission is not necessary. Any new data will be buffered until the interface is in Idle state.
For a PS/2 keyboard, up to 16 bytes of key strokes can be buffered for transmission to the Controller. For a PS/2 mouse, only the current movement packet is stored for transmission.
Transmission from Controller to PS/2 Device
For the host processor to send a command to the PS/2 device via the PS2_W Controller, the stb flag in the Wishbone Control register (WCREG.1) must be set.
To effect transmission, the PS2_W Controller must then enter the Host Send Request state. This is achieved by taking the following actions:
- the PS2CLK line is first taken Low for at least one clock period (entering Inhibit Transmission state)
- the PS2DATA line is then taken Low (providing the Start bit of the frame to be transmitted)
- the PS2CLK line is then released (still holding PS2DATA Low).
The PS/2 device regularly checks the data and clock lines for this state and when detected, starts to generate the PS2CLK signal.
When sending data from the Controller to the PS/2 device, the PS2 frame consists of 10 fields. The order of these fields is shown in Table 3.
Table 3. PS2 Frame (from Controller to PS/2 device).| Start | Data 0 | Data 1 | Data 2 | Data 3 | Data 4 | Data 5 | Data 6 | Data 7 | Parity |
Start | – | indicates the start of a transmitted frame. This is always a '0'. |
Data0-Data7 | – | the actual data bits. The least significant bit (Data0) is always sent first. |
Parity | – | used for error detection. Odd parity is used. Therefore, if the number of '1's in Data0-7 is even, the Parity bit is set (1). If the number of '1's is odd, the Parity bit is cleared (0). |
Figure 2 shows the timing for this frame transmission. The PS/2 device reads each bit in the frame on the falling edge of the clock signal.
Figure 2. Transmission of data from Controller to PS/2 device.
After transmission of the Parity bit, the PS2DATA line is released back to its idle state. The PS/2 device monitors this line and when it has detected no change from the idle state for at least one clock period, it takes the line Low again for a single clock period. This tells the Controller that the data has been fully received by the device, i.e. an acknowledgement. Both PS2CLK and PS2DATA lines are released to their idle state. The Controller can initiate another transmission request at this point.
If the PS/2 device does not detect the release of the PSDATA line after the reception of the parity bit, it will continue to provide the PS2CLK signal. Once the PSDATA line is finally released, the device will pull it Low and send the command to 'retransmit byte'. On reception of this byte, the PS2_W Controller should then retransmit the previous byte.
The Controller can inhibit transmission of data at any time before the PS/2 device sends the ACK signal, by taking the PS2CLK line Low for at least one clock period.