PS2_W - Operational Overview

The PS2_W Controller provides the Wishbone interface between a processor (host) on the one side and a PS/2 device (keyboard or mouse) on the other. The host processor sends data to and receives data from the PS2_W Controller, through the Controller's internal Wishbone Data register (WDREG).
 

Transmission from CPU to PS/2 Device

The CPU sends data to the PS2_W Controller through the Wishbone Data register (WDREG). Once a byte of data is written to this register, the Controller puts it into its transmit buffer.

The PS2_W Controller stores this data until the stb flag is set in the Wishbone Control register (WCREG.1).

Once the stb flag is set, the PS2_W Controller prepares a single byte of data for transmission. The byte of data is organized into a frame. The Controller also generates a parity bit (odd parity) for the frame —- necessary for error checking when a frame of data is received by the PS/2 device.

The frame of data is then transmitted to the connected PS/2 device, over the bidirectional PS2DATA bus (in the schematic design, this data leaves the PS2_W Controller on the PS2DATAO pin). It should be noted that only a single byte of data can be sent at any one time. To send an additional byte of data, the host CPU should read the state of the busy flag (WCREG.0) and once it is cleared, write a new byte of data into the Wishbone Data register and set the stb flag in the Wishbone Control register.
 

Transmission from PS/2 Device to CPU

Data sent from the PS/2 device over the PS2DATA bus arrives at the PS2_W Controller on the PS2DATAI pin. The received data, previously clocked in on the falling edge of the PS2CLK signal, is then synchronized with the clock signal internal to the FPGA device.

Each received data frame is shifted out through the Receive Shift Register. Parity checking is then performed to ensure the integrity of the data.

If the parity check reveals no errors, the PS2_W Controller then generates an interrupt signal to the CPU – taking the INT_O output High. INT_O stays High for at least 13 periods of the external CLK_I signal, in order for the CPU to 'see' the interrupt. This alerts the CPU to the fact that a byte of data has been received from the PS/2 device.

The CPU then reads the data from the PS2_W Controller's internal Wishbone Data register (WDREG).

The CPU can interrogate the state of the PS2_W Controller at any time by reading the state of the busy flag in the Wishbone Control register (WCREG.0). When this bit is High, the Controller is either transmitting data to, or receiving data from, the PS/2 device.