PS2_W - Accessible Internal Registers
All Wishbone communication is carried out through two dedicated registers – the Wishbone Control register (WCREG) and Wishbone Data register (WDREG) respectively.
Wishbone Control Register (WCREG)
Address: 0h
Access: Read and Write
Value after Reset: 00h
The Wishbone Control register holds the current state of the Controller and is used to control transmission of data to the PS/2 slave device.
MSB LSB | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | stb | busy |
Bit | Symbol | Function |
---|---|---|
WCREG.7 | - | Not Used. Returns '0' when read. |
WCREG.6 | - | Not Used. Returns '0' when read. |
WCREG.5 | - | Not Used. Returns '0' when read. |
WCREG.4 | - | Not Used. Returns '0' when read. |
WCREG.3 | - | Not Used. Returns '0' when read. |
WCREG.2 | - | Not Used. Returns '0' when read. |
WCREG.1 | stb | Strobe flag. This bit is set by the CPU to initiate transmission to the connected PS/2 slave device. This bit is automatically cleared by the Controller when it starts transmission. |
WCREG.0 | busy | Busy flag. This bit is set when the PS2_W Controller performs the requested task. This bit is ignored when writing to this register. |
Wishbone Data Register (WDREG)
Address: 1h
Access: Read and Write
Value after Reset: 00h
When written to, the Wishbone Data register writes data to be transmitted to the slave PS/2 device, into the Controller's transmit buffer.
When read, the register returns whatever data is currently in the Controller's receive buffer.
When INT_O is asserted, reading the register returns the byte of data received from the slave PS/2 device.
MSB LSB | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
db7 | db6 | db5 | db4 | db3 | db2 | db1 | db0 |
Bit | Symbol | Function |
---|---|---|
WDREG.7 | db7 | Data Bit 7. |
WDREG.6 | db6 | Data Bit 6. |
WDREG.5 | db5 | Data Bit 5. |
WDREG.4 | db4 | Data Bit 4. |
WDREG.3 | db3 | Data Bit 3. |
WDREG.2 | db2 | Data Bit 2. |
WDREG.1 | db1 | Data Bit 1. |
WDREG.0 | db0 | Data Bit 0. |