OpenBus Tutorial - Configuring the Interconnect Components

Configuration of an Interconnect component in the OpenBus System is a far more streamlined process in comparison to its schematic-based counterpart, WB_INTERCON. The system handles much of the configuration 'behind the scenes' as it were, so information such as data bus width, addressing mode and device type, no longer require user-definition.

There is no manual addition/deletion of devices to/from the Interconnect. If a link exists between a peripheral and the Interconnect, then the device will automatically be added.

There is also no manual definition of the Master Address Size. This too is taken care of in the background, dependent on which port of the processor the Interconnect is linked – IO (24-bit) or MEM (32-bit).

There are, in fact, only three pieces of information required to complete the configuration of the Interconnect for each slave device – the Base Address, the Decoder Address Width and the Address Bus Size. Default information for each comes directly from the peripheral component itself.

Peripheral I/O Interconnect

We will now configure the Interconnect component that is linked to the TSK3000A processor's IO port.

1. Double-click on the Interconnect component designated INTERCON_IO to access the Configure OpenBus Interconnect dialog. The decoder address width for each peripheral is set to 8 bits by default and we can leave this as it is the same in the original design. The address bus sizes – the number of address bits required to drive each device – are also set correctly.
    
2. In the Address field for the IEEE754 Floating Point Unit (FPU) peripheral, enter the value 0xFF000000
    
3. In the Address field for the VGA 32-Bit TFT Controller (VGA) peripheral, enter the value 0xFF100000
    
4. In the Address field for the SPI (SPI) peripheral, enter the value 0xFF200000
    
5. In the Address field for the Port IO (GPIO) peripheral, enter the value 0xFF300000

The settings in the dialog should now appear as those in Figure 1.

Figure 1. Configured Interconnect component (INTERCON_IO).

Memory Interconnect

We will now configure the Interconnect component that is linked to the TSK3000A processor's MEM port.

1. Double-click on the Interconnect component designated INTERCON_MEM to access the Configure OpenBus Interconnect dialog. The decoder address width for the memory controller is set to 8 bits by default and we can leave this as it is the same in the original design. The address bus size – the number of address bits required to drive the controller – is also set correctly.
    
2. In the Address field for the SRAM Controller (XRAM) peripheral, enter the value 0x01000000.

The settings in the dialog should now appear as those in Figure 2.

Figure 2. Configured Interconnect component (INTERCON_MEM).

See Also