KEYPADA_W - Operational Overview

Operation of the Keypad Controller within a design is very straightforward. The processor to which the Controller is connected simply monitors the INT_O output from the Controller. When the INT_O signal goes High – corresponding to a valid key being pressed on the Keypad – the processor will perform a Wishbone read of the KEYPADA_W's internal KEYREG register. The KEYPADA_W will send a byte of data, appearing at the processor's io_DATA_I input, the low order nibble of which identifies the key that has been pressed. An interrupt routine would then be entered within the embedded code running on the processor and io_DATA_I[3..0] used as parametric input.

Scanning the Keypad Matrix

The Controller tests the keypad matrix for a valid key press, continuously, using the 4-bit ROW and COL buses. The detail of the keypad matrix and how these 4-bit signals are used can be seen in Figure 1.

Figure 1. Keypad matrix and distribution of ROW and COL bus signals (on the NanoBoard-NB1).

The Controller sends a 4-bit value on the ROW bus, which is simply the decoded and inverted output of a 2-bit binary counter.

The binary counter is clocked at a rate of 31 Hz. The value on the ROW bus is therefore changed approximately every 32 milliseconds. This provides continuous scanning of the matrix, by effectively testing each row in sequence and in a cyclic fashion.

Table 1 summarises the value sent to the keypad matrix on the ROW bus, based on the output of the binary counter.

The state of the keypad matrix is returned on the 4-bit COL bus. If a key has been pressed within a column, the corresponding bit on the bus will be a '0', otherwise the value '1' will be returned.

If no key has been pressed, all columns will return a '1'. The 4-bit value on the COL bus will therefore be 1111. The INT_O signal will remain Low in this case and the Controller will continue with its scanning of the matrix, one row at a time.

If a key is pressed on the Keypad, the value on the COL bus will reflect the column in which the key was pressed. This value is passed to the Controller's debounce circuitry, to validate whether a key has been truly pressed.

The scan rate is approximately eight times slower than the clock used for the internal debounce circuitry. This ensures that the debounce test is completed before the next row of the matrix is tested.

Validating a Key Press - Debounce

The Keypad Controller has inherent key debouncing. The Controller's debounce circuitry takes as input the 4-bit signal on the COL bus. If the value on the bus remains unchanged for at least 4 cycles of a 244Hz clock, the key press is deemed to be a valid one.

Once a 'valid key down' situation has been recognized, the output of the debounce circuit (essentially a 4-input AND gate) will go High. This signal is used, in turn, to clock the respective latches for the INT_O and Key signals – setting the INT_O signal High, to flag to the processor that a valid key has been pressed on the Keypad and presenting the 4-bit data which specifies the pressed key, on the Key bus.

When the host processor performs a read of the KEYREG register, the value sent from the KEYPADA_W on the DAT_O bus is formed by joining the 4-bit Key bus (low order nibble of DAT_O) with a 4-bit bus connected to Ground (high order nibble of DAT_O).

Composing the Pressed Key Data Value

The return value from the Keypad Matrix is, simultaneous to the debounce testing, inverted and passed through a 4-bit to 2-bit Encoder.

If the debounce circuitry determines the key press to be valid, the current 2-bit output value from the Encoder will be used to reflect the column in which the pressed key resides. This value is then used when composing the 4-bit Row-Column data value presented to the processor as the low order nibble of the data byte sent to its io_DATA_I input.

Table 2 summarizes the 2-bit Column portion of the Key signal, based on the value returned on the COL bus.

When the key-press has been recognized as valid, the current row being tested is the one used to reflect the row in which the pressed key resides. As the clock used for the debounce circuit is eight times faster than the clock used to provide scanning of the rows, there is no possibility of the next row being tested before the debounce validation has completed.

The 2-bit Row portion of the Key signal is therefore the current output of the Binary Counter.

The separate 2-bit Row and Column values are then combined to form the single 4-bit Key value, with bits 3..2 representing the Row and bits 1..0 representing the Column. This is the value that the processor will read – appearing as the low order nibble of the byte of data sent to its io_DAT_I input – after being alerted to a valid key press by INT_O going High. This gives the processor the Row-Column intersect within the matrix, for the key that was pressed. The processor can then take the appropriate action based upon its embedded code.

The INT_O signal will remain High, until either an external reset signal has specifically been sent to the Controller – appearing at its RST_I input – or if the processor performs a write to either of the two internal registers. The Controller will then automatically take INT_O Low and resume scanning of the keypad matrix.