KEYPADA_W - Accessible Internal Registers

The following sections detail the internal registers for the KEYPADA_W, accessible from the host processor.

Key Register (KEYREG)

Address: 0

Access: Read Only

This register is used to store the 4-bit value representing the key that has been pressed on the Keypad. Bits 3..2 represent the Row (sourced from the output of the Binary Counter) and bits 1..0 represent the Column (sourced from the output of the 4-bit to 2-bit Encoder).

When reading this register, the value in the register will appear as the low order nibble on the DAT_O bus presented to the processor. The upper nibble of the data byte will be "0000".

Valid Key Register (VALKEYREG)

Address: 1

Access: Read Only

This register is used to latch the output of the Debounce circuit. If a valid key has been pressed on the Keypad, the register will contain the value '1'. Otherwise it will contain a '0'.

When reading this register, the value in the register will appear as bit 0 on the DAT_O bus presented to the processor. The upper 7 bits of the data byte will be '0'.

The output of the register is also passed to the INT_O output – to flag to the processor that a valid key has been pressed. This interrupt is cleared by either an external reset (on the RST_I line), or by writing to either of the two internal register addresses. Although the registers can't actually be written to – as the Controller has no DAT_I input – simply taking the processor's io_STB_O, io_CYC_O and io_WE_O lines high will result in clearing the VALKEYREG register and therefore taking the INT_O line Low.