FPGA Design
Use the following links to browse through the frequently asked questions relevant to this area of soft design. For more in-depth, visual answers to commonly posed questions, use the links to the corresponding training videos, listed on the right.
- Which versions of FPGA Vendor tools are supported by Altium Designer?
- Is there a quick way to get Harness Entry spacing the same as the port-plugin components I am connecting to?
- I have an FPGA device that is not supported by Altium Designer. How can I attach a BSDL file to enable correct operation of the Hard JTAG chain?
- What do I do if my FPGA device is not supported by the system, and I have no BSDL file for it?
- Is there a listing of all physical devices supported by Altium Designer?
Which versions of FPGA Vendor tools are supported by Altium Designer?
The verions of vendor tools supported by Altium Designer, and links to each vendor's downloadable tools, can be found in the (Vendor Tools) area of the Altium website. This page can be accessed directly from within Altium Designer. With the Devices view active (View » Devices Views), simply choose the Vendor Tool Support entry on the main Tools menu.
Is there a quick way to get Harness Entry spacing the same as the port-plugin components I am connecting to?
The harness entries in the harness definitions generated by the OpenBus System have been ordered to match the order of pins in port-plugin components. However, there may be spaces between pins in the port-plugin components, whereas there are no spaces between the harness entries of the harness connector.
When placing or moving a harness connector, the spacing between the harness entries can be made to match the spacing between the pins of the port-plugin component by hovering the harness connector over the port-plugin component (ensuring that the cursor is above the port-plugin component) and then pressing the Insert key.
I have an FPGA device that is not supported by Altium Designer. How can I attach a BSDL file to enable correct operation of the Hard JTAG chain?
A BSDL file is attached to a Generic JTAG Device by right-clicking on the icon for the device, in the Hard Devices chain of the Devices view, and choosing the Configure JTAG ID Mapping command. The Generic JTAG Device dialog will appear.
Simply click the Add button in the BSDL File Links region of the dialog – the entry enter BSDL filename
will appear in the list. Either type the filename directly or click the folder icon at the right of the field to navigate to the required file. By default, the path is set to the \Library\BSDL\Generic
folder of the installation. BSDL files should be placed in this folder.
The system will use the information in the file – including the device's ID Code and Instruction Register Length – to correctly configure the Hard JTAG chain.
What do I do if my FPGA device is not supported by the system, and I have no BSDL file for it?
Right-click on the icon for the device, in the Hard Devices chain of the Devices view, and choose the Configure JTAG ID Mapping command. In the Generic JTAG Device dialog that appears, simply set the correct instruction length for the device. With this set, the JTAG system can continue to communicate to other devices in the Hard JTAG chain.
Is there a listing of all physical devices supported by Altium Designer?
Yes. From the Devices view (View » Devices View) use the Tools » Browse Physical Devices command. The Browse Physical Devices dialog will appear, from where you can browse the range of physical FPGA devices, CPLDs and configuration devices, supported by Altium Designer, available across different device families and from different Vendors. Available (and supported) devices will have a pin number value entered in the main device availability grid. Devices that do not exist are represented by a hyphen character '-'.
At the bottom-left of the dialog, click the Device Support Report button. A full report (AltiumDesignerDeviceSupport.Txt
) listing all physical devices supported by Altium Designer will be generated, listing devices by vendor and device family. You will be given the option to include or exclude device details (package, pin count, user I/O pins, etc) for the report as required. Once generated, the report will open as the active document in the main design window.