EMAC8_W, EMAC8_MD_W - Internal Wishbone Registers
Contents
To simplify communications with internal EMAC registers, and to reduce the number of addresses, all Wishbone communication is carried out through three dedicated registers – the Wishbone Low Address register (WAREG_L), Wishbone High Address register (WAREG_H) and Wishbone Data register (WDREG) respectively.
To access any of the Controller's internal registers or buffers, the host processor must write to the two Wishbone Address registers with a valid EMAC register address and then either write data to or read data from, the Wishbone Data register.
When writing, data will be written directly to the internal EMAC register or Transmit Buffer location addressed by the Wishbone Address registers. When reading, the data in the Wishbone Data register mirrors that currently stored in the internal EMAC register or Receive Buffer location addressed by the Wishbone Address registers.
Wishbone Low Address Register (WAREG_L)
Address: 2h
Access: Read and Write
Value after Reset: 00h
This 8-bit register is used to hold bits 7..0 of the 11-bit address of the Controller's internal register that you wish to write to/read from.
MSB LSB | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ab7 | ab6 | ab5 | ab4 | ab3 | ab2 | ab1 | ab0 |
Bit | Symbol | Function |
---|---|---|
WAREG_L.7 | ab7 | Address Bit 7 |
WAREG_L.6 | ab6 | Address Bit 6 |
WAREG_L.5 | ab5 | Address Bit 5 |
WAREG_L.4 | ab4 | Address Bit 4 |
WAREG_L.3 | ab3 | Address Bit 3 |
WAREG_L.2 | ab2 | Address Bit 2 |
WAREG_L.1 | ab1 | Address Bit 1 |
WAREG_L.0 | ab0 | Address Bit 0 |
Wishbone High Address Register (WAREG_H)
Address: 3h
Access: Read and Write
Value after Reset: 00h
This 8-bit register is used to hold bits 10..8 of the 11-bit address of the Controller's internal register that you wish to write to/read from.
MSB LSB | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | ab10 | ab9 | ab8 |
Bit | Symbol | Function |
---|---|---|
WAREG_H.7 | - | Not used. Returns 0 when read |
WAREG_H.6 | - | Not used. Returns 0 when read |
WAREG_H.5 | - | Not used. Returns 0 when read |
WAREG_H.4 | - | Not used. Returns 0 when read |
WAREG_H.3 | - | Not used. Returns 0 when read |
WAREG_H.2 | ab10 | Address Bit 10 |
WAREG_H.1 | ab9 | Address Bit 9 |
WAREG_H.0 | ab8 | Address Bit 8 |
Wishbone Data Register (WDREG)
Address: 0h
Access: Read and Write
Value after Reset: 00h
This 8-bit register is used as a buffer to write to, or read from, any of the Controller's internal registers or buffers.
MSB LSB | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
db7 | db6 | db5 | db4 | db3 | db2 | db1 | db0 |
Bit | Symbol | Function |
---|---|---|
WDREG.7 | db7 | Data Bit 7 |
WDREG.6 | db6 | Data Bit 6 |
WDREG.5 | db5 | Data Bit 5 |
WDREG.4 | db4 | Data Bit 4 |
WDREG.3 | db3 | Data Bit 3 |
WDREG.2 | db2 | Data Bit 2 |
WDREG.1 | db1 | Data Bit 1 |
WDREG.0 | db0 | Data Bit 0 |