Configuring the Interconnect Component

Configuration of an Interconnect component is performed using the Configure OpenBus Interconnect dialog (Figure 1). Access this dialog by right-clicking over the component and choosing the Configure command from the menu that appears. Alternatively, double-click on the component to access the dialog directly.

Figure 1. Configuration dialog for the Interconnect component.

Use this dialog to define the slave devices that you wish to connect to the processor. If you are familiar with configuration of the WB_INTERCON component in the schematic world, you will appreciate the reduced level of information required to configure the Interconnect component. The OpenBus System handles much of the configuration for you, so information such as data bus width, addressing mode and device type are no longer defined manually.

There is no manual addition/deletion of slave devices to/from the Interconnect. If a link exists between a slave peripheral device and the Interconnect component, then that device will automatically be added and appear listed in the dialog.

There is no manual definition of the Master Address Size. This too is taken care of in the background, dependent on which port of the processor the Interconnect is linked – IO (24-bit) or MEM (32-bit).

There are, in fact, only three pieces of information required to complete the configuration of the Interconnect for each slave device – Address, Number of bits to decode and Size. Default information for each comes directly from the linked peripheral component itself.

Address

This address (also referred to as the Base Address) is used to map the slave device into a processor's address space (either peripheral I/O or external memory). The size of the address depends on whether the device linked to the Interconnect is slave peripheral I/O or slave memory:

• For a slave peripheral I/O device, it is a 24-bit value, entered as a 6-digit hexadecimal number. As the processor peripheral I/O space is in the range 0xFF000000 to 0xFFFFFFFF, the entry in the dialog includes the top byte 0xFF prefix as a guiding reminder of this.

• For a slave memory device, the base address is a 32-bit value, entered as an 8-digit hexadecimal number.

When adding slave peripheral I/O devices, default base addresses are assigned, starting at 0xFF000000 for the device connected to port m0 and incremented in steps of 0x10000. When adding slave memory devices, addresses are assigned starting at 0x01000000 for the device connected to port m0 and incremented in steps of 0x1000000. You must specify Address values for each device, in accordance with design requirements.
 

Number of Bits to Decode

This value (also referred to as the Decode Address Width) determines how many bits of the incoming address line, from the processor, are used to identify and select the correct slave device for subsequent communications.

At a high level, if you visualize the Interconnect component in terms of a multiplexer, then a slave device will be accessed by the processor over the single bus interface when it is selected for communications. This selection is achieved by comparing the n (number of bits to decode) top bits of the address written by the processor, with the n top bits of the Base Address defined for each slave device. When a match is found, the processor begins communications with that slave immediately. The required n-bit comparators – one per attached slave device – are generated automatically during the synthesis phase.

At a low level, when communication between devices takes place over a Wishbone Bus, it is the STB_O and CYC_O lines that initiate the start of a valid data cycle and transfer. The bus from the processor is connected through to each master port on the Interconnect component. The STB_O and CYC_O lines of each port are conditioned to only go active if:

• the corresponding STB_I and CYC_I lines of the Interconnect's slave port are High AND

• the associated comparator for the interface yields a High output as a result of address bit comparison.

To illustrate this, consider an OpenBus System in which three slave peripheral I/O devices are connected to a processor through an Interconnect component. 2 bits are used to decode the incoming address from the processor. Table 1 lists the three devices, along with their base addresses and the value that will cause the associated comparator to give a High output.

Figure 2 illustrates more closely what is going on inside the Interconnect component with regards to the role of the comparator for each slave device interface. Only STB and CYC signals are shown, all other bus signals have been excluded for clarity.

Figure 2. Address decoding for slave devices attached to an Interconnect component.

The number of address decode bits specified determines the number of slave devices that can be connected to the Interconnect component. For n bits, 2^n^ devices can be addressed. For example, if you specify 3 bits, the resulting 8 possible values allow for 8 slave devices to be attached to the Interconnect component.

Using a smaller number of bits for comparison will lower the hardware overhead, but also limit the number of slave devices that can be used. The optimal scenario would be to make the decode address width as small as possible while allowing enough slave devices to be added to the Interconnect component, in accordance with design requirements.

For each peripheral I/O and memory device supported for use in an OpenBus System design, the number of address decode bits is set, by default, to 8. In terms of decoding, this means:

• For peripheral I/O devices, the top 8 bits of the address from the processor (ADR_I[23..16]) are compared against the top 8 bits of the 24-bit value defined for each device's Base Address.

• For memory devices, the top 8 bits of the address from the processor (ADR_I[31..24]) would be compared against the top 8 bits of the 32-bit value defined for each device's Base Address.

For more information on setting the number of address decode bits and which base addresses to assign to each slave device, see Address Decode Bits Vs Base Address - a Juggling Act.

Size

This value (also referred to as Address Bus Size) defines the number of address bits required to drive the connected slave device. For OpenBus components (peripherals and memory controllers) this information is sourced automatically from the component itself and typically should not need to be modified.