CANB_W - Pin Description
The pinout of the CAN Controller has not been fixed to any specific device I/O, thereby allowing flexibility with user application. The CAN Controller contains only unidirectional pins – inputs or outputs.
The following pin description is for the CANB_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. CANB_W pin description.| Name | Type | Polarity / Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External system clock |
| RST_I | I | High | External system reset. A High state on this pin for two clock cycles while the system clock (CLK_I) is running, resets the component. |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 7 | Address bus, used to directly select an internal CAN register of the component for writing to/reading from. |
| DAT_O | O | 8 | Data to be sent to host processor |
| DAT_I | I | 8 | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| INT_O | O | High | Interrupt output |
| INT_I | I | High | Interrupt input |
| CAN BUS Interface Signals | |||
| RXD | I | - | Input from the physical CAN bus line |
| TXEN | O | Low | This signal is used to enable tristate output buffers |
| TX0, TX1 | O | - | Outputs from the Controller output drivers to the physical bus line. Function depends on Output Mode selected by OCMODE bits in Output Control Register. |
| CLK_OUT | O | Rise | Clock output signal. This signal is derived from the system CLK_I signal via the programmable divider. The Clock Off bit within the Clock Divider Register allows this pin to be disabled. |
| OUTCTRL | O | 6 | Signals used to control output transistors. |