CANB_W - Accessible Internal Registers (Summary)
Frozen Content
The following table lists all of the internal CAN registers.
Location in CAN address space | Parent hardware structure | Register | |
---|---|---|---|
00h | Interrupt and Status Control Unit (ISC) | Mode register (MOD) | |
01h | Interrupt and Status Control Unit (ISC) | Command register (CMR) | |
02h | Interrupt and Status Control Unit (ISC) | Status register (SR) | |
03h | Interrupt and Status Control Unit (ISC) | Interrupt register (IR) | |
04h | Interrupt and Status Control Unit (ISC) | Interrupt Enable register (IER) | |
05h | - | - | |
06h | Bit Timing Logic (BTL) | Bus Timing Register 0 (BTR0) | |
07h | Bit Timing Logic (BTL) | Bus Timing Register 1 (BTR1) | |
08h | Bit Timing Logic (BTL) | Output Control register (OCR) | |
09h | - | - | |
0Ah | - | - | |
0Bh | Acceptance Filter (AF) | Arbitration Lost Capture register (ALC) | |
0Ch | Error Management Logic (EML) | Error Code Capture register (ECC) | |
0Dh | Error Management Logic (EML) | Error Warning Limit register (EWL) | |
0Eh | Error Management Logic (EML) | RX Error Counter register (REC) | |
0Fh | Error Management Logic (EML) | TX Error Counter register (TEC) | |
10h - 13h | Transmit Buffer (TB) / FIFO Control Unit / Acceptance Filter (AF) | Acceptance Code registers (ACR0 - ACR3) | Transmit Buffer register (TB0 - TB12) Receive Buffer register (RB0 - RB12) |
14h - 17h | Transmit Buffer (TB) / FIFO Control Unit / Acceptance Filter (AF) | Acceptance Mask registers (AMR0 - AMR3) | |
18h - 1Ch | Transmit Buffer (TB) / FIFO Control Unit | - | |
1Dh | FIFO Control Unit | Message Counter (MC) | |
1Eh | FIFO Control Unit | Receive Buffer Start Address register (RBSA) | |
1Fh | Bit Timing Logic (BTL) | Clock Divider register (CDR) | |
20h - 5Fh | FIFO Control Unit | Receive Buffer register (RB0 - RB12) (direct read/write) | |
60h - 6Ch | Transmit Buffer (TB) | Transmit Buffer register (TB0 - TB12) (direct read/write) | |
6Dh - 6Fh | - | - | |
70h - 7Fh | - | - |