BT656 - Accessible Internal Registers

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The following sections detail the internal registers for the BT656 Controller that can be accessed from the host processor.

Mode Register (MODE)

Address: 0h

Access: Read and Write

Value after Reset: 0000_0014h

This register is used to set the operational mode of the Controller.

Table 1. The MODE register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                                                  5
4
3
2
1
0
-
cm3
cm2
cm1
sfc
run
Table 2. The MODE register bit functions.
Bit
Symbol
Function
MODE.31..MODE.5
-
Not Used.
MODE.4
cm3
Color Mode selection bits. Used to define the color scheme to be used when converting the YCbCr color space of the BT.656 stream into RGB or Grey scale. See Table 6 for a full description of the modes and the corresponding assignment of these bits.
MODE.3
cm2
MODE.2
cm1
MODE.1
sfc
Single Frame Capture bit. A single frame will be captured after this bit is set. This bit will be reset by hardware once capture of the frame has completed.
MODE.0
run
Run mode.

1 = Run continuously, starting with the next complete frame after this bit is set.
0 = Stop. If the Controller is in the process of acquiring a frame, it will proceed with conversion of the frame and then stop.

Bits cm3..cm0 are used to select the color mode as follows:

Table 3. Color Mode selection.
cm3:cm2:cm1
Color Mode
001

Grey – 8 bits per pixel (1 byte per pixel)

010

Grey – 16 bits per pixel (2 bytes per pixel)

110

Grey – 32 bits per pixel (4 bytes per pixel)

100

Color – 8 bits per pixel (1 byte per pixel)

101

Color – 16 bits per pixel (2 bytes per pixel)

110

Color – 32 bits per pixel (4 bytes per pixel)

Note: Bit assignments 000 and 111 are invalid and will result in the output being disabled.

The sfc and run bits together define the four operating modes in which the Controller can be placed, as listed in Table 4.

Table 4. Controller operating modes.
sfc:run
Operating Mode
00

Disabled

01

Run

10

Single Frame

11

Run (Run mode overrides Single Frame mode)

Status Register (STATUS)

Address: 1h

Access: Read only

Value after Reset: 0000_0014h

This register is used to determine the current state of the Controller.

Table 5. The STATUS register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                                                  5
4
3
2
1
0
-
cm3
cm2
cm1
sft
run
Table 6. The STATUS register bit functions.
Bit
Symbol
Function
STATUS.31..STATUS.5
-
Not Used.
STATUS.4
cm3
Color Mode setting. These bits reflect the color scheme chosen to be used when converting the YCbCr color space of the BT.656 stream into RGB or Grey scale. See Table 6 for a full description of the modes and the corresponding assignment of these bits.
STATUS.3
cm2
STATUS.2
cm1
STATUS.1
sft
Single Frame Triggered flag. This bit is set if the sfc bit in the MODE register (MODE.1) is High, the run bit in the MODE register (MODE.0) is Low, and a single frame of video data is being captured.
STATUS.0
run
Controller Running flag. This bit is set if the run bit in the MODE register (MODE.0) is High. This bit is updated at the start of a new frame.

Start Register (START)

Address: 2h

Access: Read and Write

Value after Reset: 0000_0000h

This register is used to store the start address for the video buffer in external memory – i.e. the memory address of the first pixel (0, 0) – which is accessed through the Controller's Wishbone Master interface. The start address must be a multiple of 4.

The width of the memory used for the video buffer is actually 32 bits. When addressing locations in this memory, the 30-bit address value is sent on the WBM_ADR_O line as bits 31..2, with bits 1..0 always zeros.

Size Register (SIZE)

Address: 3h

Access: Read and Write

Value after Reset: 0000_0000h

This register is used to store the 21-bit value for the size of the video buffer in which the decoded (and reformatted) video image will be stored. Although the value for the actual size can be up to 2Mb (21 bits), only bits 20..2 are used, with bits 1..0 set to '0'.

The BT656 Controller never writes outside of the available memory 'window' defined by the START and SIZE registers. The size must be a multiple of 4.

Bytes Per Line Register (BPL)

Address: 4h

Access: Read and Write

Value after Reset: 0000_05A0h

This 13-bit register is used to set the number of bytes per line for the output device onto which the video memory image will be displayed. The value stored is defined by the following expression:

BPL register value = Line_Size * BPP,

where,

Line_Size is the line size of the output device, in pixels.

BPP is the number of bytes per pixel, in accordance with the color mode chosen for the output.

With regard to the memory layout of the captured image, the address of each new line will be at a multiple of the value stored in this register. If we represent the value of the START register by start_address, and the value of the BPL register with bytes_per_line, then the addresses in memory would be:

Line 1 at start_address

Line 2 at start_address + bytes_per_line

Line 3 at start_address + 2*bytes_per_line, and so on..
 

If the width of the output device (e.g. VGA) differs from the width of the incoming video, there must be a gap between each line, to get each subsequent line of the incoming video underneath the last.

Visible Bytes Per Line Register (VBPL)

Address: 5h

Access: Read and Write

Value after Reset: 0000_05A0h

This register is used to store the 12-bit value for the number of bytes per line actually written into memory, after any horizontal scaling. The value is calculated as follows:

VBPL register value = (Line_Size * BPP) / (x_zoom + 1),

where,

Line_Size is the line size of the output device, in pixels.

BPP is the number of bytes per pixel, in accordance with the color mode chosen for the output.

x_zoom is the integer representation of the 4-bit x-scaling value set in the SCALE register (SCALE3..0).

Scaling Register (SCALE)

Address: 6h

Access: Read and Write

Value after Reset: 0000_0000h

This register is used to store scaling information, to be applied to the captured image.

Table 7. The SCALE register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                12 11                        8 7                        4 3                        0
-
frame_rate
y_zoom
x_zoom
Table 8. The SCALE register bit functions.
Bit
Symbol
Function

SCALE.31..SCALE.12

-

Not Used.

SCALE.11..SCALE.8

frame_rate

Sets the number of frames to be skipped after each captured frame:

0000 = each frame captured
0001 = capture each 2nd frame
0010 = capture each 3rd frame
.
.
.
1111 = capture each 16th frame.

SCALE.7..SCALE.4

y_zoom

Sets the Y-direction zoom factor:

0000 = no zoom
0001 = discard 1 line after each captured line (1/2 height)
0010 = discard 2 lines after each captured line (1/3 height)
.
.
.
1111 = discard 15 lines after each captured line (1/16 height).

SCALE.3..SCALE.0

x_zoom

Sets the X-direction zoom factor:

0000 = no zoom
0001 = discard 1 pixel after each captured pixel (1/2 width)
0010 = discard 2 pixels after each captured pixel (1/3 width)
.
.
.
1111 = discard 15 pixels after each captured pixel (1/16 width).

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