Xilinx Place and Route Tools Configuration
The place and route tools are all accessed and configured from the Build stage of the Process Flow associated to the target physical device in the Devices view. To enable and display the Process Flow when the target device is a Xilinx FPGA you must:
- Have the appropriate Xilinx vendor tools installed – either the full tool suite or the freely downloadable version available from the Xilinx website – and
- Your design must be configured for a valid Xilinx target architecture. This is done by including a suitable device constraint in a project constraint file, which belongs to a current project configuration (Project » Configuration Manager).
Build Options
The Build process allows interface with Xilinx tools and produces the bitstream (BIT) file to download into your FPGA. By clicking on the down arrow, a list of individual steps used to complete the Build process can be found (Figure 1).
Figure 1. Constituent stages of the Build process.
Click the Options icon () adjacent to each stage to configure that feature. Errors or design rules that are not allowed for your target architecture or in the design will be picked up at each stage of the Build process. The location in the design and the error or warning is logged in a report file, accessed by clicking on the appropriate Report icon ().
For advanced users who want more control over the options passed to the Xilinx tools, each stage in the Build process is linked to a script file located in the \System folder of the installation. Be aware that these scripts are defaulted to standard optimization – any changes should be carefully applied in consultation with the Xilinx Development System Reference Guide. Individual Build stages, options and the corresponding default script files are described in the following sections.
Translate Design
This stage invokes the Xilinx NGDBuild tool, translating the EDIF output from the FPGA project synthesis process to a Xilinx Native Generic Database (NGD) file and Xilinx Project Navigator project (NPL) file. In this process, a logic design rule check is also run to confirm that the design is fit for mapping to any target FPGA. For more information on options available with this process refer to chapter 6 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_NGBuild.Txt script file. NGDBuild switches can be configured in this file, in accordance with the Xilinx documentation. The Xilinx project can be opened in the Xilinx Project Navigator if required.
Map Design to FPGA
This stage invokes the Xilinx MAP tool, mapping the NGD file to the logic available in your target Xilinx FPGA. In this process, a physical design rule check is run to find physical and logical errors that may be present, depending on your target FPGA. The output of this process is an NCD (Native Circuit Description) file. For more information on options available with this process refer to chapter 8 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_MAP.Txt script file. Map switches can be configured in this file, in accordance with the Xilinx documentation.
Place and Route
This stage invokes the Xilinx PAR tool and uses the NCD file output from the MAP process to place and route. A placed and routed NCD file is produced, suitable for the bitstream generator. For more information on options available with this process refer to chapter 10 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_PlaceAndRoute.Txt script file. PAR switches can be configured in this file, in accordance with the Xilinx documentation.
Timing Analysis
This stage invokes the Xilinx Trace (timing reporter and evaluator) tool. This conducts static timing analysis on the design, based on the input timing constraint. It verifies that the design meets the timing constraints, generating a report on the analysis. For more information on options available with this process refer to chapter 13 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_Trace.Txt script file. Trace switches can be configured in this file, in accordance with the Xilinx documentation. Timing analysis can be switched off if required, click on the Timing Analysis Options icon.
Make BIT File
This stage invokes the Xilinx BitGen tool to produce a bitstream (BIT) file from the placed and routed design (NCD) file. The BIT file is used to download and program the FPGA, or to create a PROM file in the Make PROM File stage. For more information on options available with this process refer to chapter 15 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_BitGen.Txt script file. BitGen switches can be configured in this file, in accordance with the Xilinx documentation.
Make PROM File
This optional stage is used to generate a program file for a Xilinx configuration device. It is available once a target PROM has been selected by clicking on the Options icon. It invokes the Xilinx PromGen tool, whose output format is dependent on the selected target device. For more information on options available with this process refer to chapter 16 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_PromGen.Txt script file. PromGen switches can be configured in this file, in accordance with the Xilinx documentation.