Xilinx Configuration Device - Generating the Configuration File

Frozen Content

Firstly, ensure that the required FPGA project is open in the Projects panel. Open the Devices view, if not already open. Ensure that the Live option is enabled as this enables the auto-board-recognition system.

The Hard Devices chainwill display any physical FPGA devices and configuration devices on the Production board, as well as an FPGA device on any Daughter Board currently plugged into the NanoBoard.

Focus the FPGA device that will be booted using the configuration file. This is done simply by clicking on the icon for the device.

In the drop-down field underneath the device's icon, make sure that the FPGA Project-Configuration combination – targeting the physical device – is correctly selected.

In the Process Flow associated to the targeted device, expand the Build section. The last entry in the Build stage menu is Make PROM File(Figure 1).


Figure 1. Accessing the command to generate a PROM file.

Click on the icon, to the far right of this menu entry. The Options for PROM File Generation dialog will appear (Figure 2).


Figure 2. Accessing the options dialog for PROM file generation.

Use the dialog to choose the target configuration device which resides on the Production board and to which the generated PROM file will be downloaded. Click inside the Value field to access a drop-down list of supported configuration devices (Figure 3).


Figure 3. Choose from a range of supported configuration devices.

The drop-down list contains devices that fall into one of two categories:

  • Configuration devices where a PROM filecan be both generated and programmed. These are all JTAG-compliant devices – a requirement in order to access the device for programming through the NanoBoard.
  • Configuration devices where only generation of the relevant PROM file is supported. These devices are not JTAG-compliant and therefore cannot be accessed for programming over the JTAG link. Special programming devices must be used to download the PROM file for these configuration devices.

Table 1 lists the supported JTAG-compliant configuration devices. Each of these devices can be reprogrammed up to 20,000 times.

Table 1. Supported JTAG-compliant configuration devices.

Device
Density
Supply Voltage
Package
XCF01S
1 Mbit
3.3V

VO20 (20-pin Plastic Thin Small Outline Package)

XCF02S
2 Mbit
3.3V

VO20 (20-pin Plastic Thin Small Outline Package)

XCF04S
4 Mbit
3.3V

VO20 (20-pin Plastic Thin Small Outline Package)

XCF08P
8 Mbit
1.8V

VO48 (48-pin Plastic Thin Small Outline Package)
FS48 (48-pin Plastic Thin Fine Pitch Ball Grid Array (0.8mm pitch))

XCF16P
16 Mbit
1.8V

VO48 (48-pin Plastic Thin Small Outline Package)
FS48 (48-pin Plastic Thin Fine Pitch Ball Grid Array (0.8mm pitch))

XCF32P
32 Mbit
1.8V

VO48 (48-pin Plastic Thin Small Outline Package)
FS48 (48-pin Plastic Thin Fine Pitch Ball Grid Array (0.8mm pitch))

XC18V01
1 Mbit
3.3V

PC20 (20-pin Plastic Leaded Chip Carrier)
SO20 (20-pin Small Outline Package)
VQ44 (44-pin Plastic Quad Flat Package)

XC18V02
2 Mbit
3.3V

PC44 (44-pin Plastic Chip Carrier)
VQ44 (44-pin Plastic Quad Flat Package)

XC18V04
4 Mbit
3.3V

PC44 (44-pin Plastic Chip Carrier)
VQ44 (44-pin Plastic Quad Flat Package)

XC18V256
256 kbit
3.3V

PC20 (20-pin Plastic Leaded Chip Carrier)
SO20 (20-pin Small Outline Package)
VQ44 (44-pin Plastic Quad Flat Package)

XC18V512
512 kbit
3.3V

PC20 (20-pin Plastic Leaded Chip Carrier)
SO20 (20-pin Small Outline Package)
VQ44 (44-pin Plastic Quad Flat Package)

Table 2 lists the the supported non-JTAG-compliant configuration devices. Each of these devices can be programmed once only.

Table 2. Supported Non-JTAG-compliant configuration devices.

Device
Density
Supply Voltage
Package
XC17V01
1 Mbit
3.3V

PC20 (20-pin Plastic Leaded Chip Carrier)
VO8 (8-pin Plastic Thin Small Outline Package)
SO20 (20-pin Small Outline Package)

XC17V02
2 Mbit
3.3V

PC20 (20-pin Plastic Leaded Chip Carrier)
PC44 (44-pin Plastic Chip Carrier)
VQ44 (44-pin Plastic Quad Flat Package)

XC17V04
4 Mbit
3.3V

PC20 (20-pin Plastic Leaded Chip Carrier)
PC44 (44-pin Plastic Chip Carrier)
VQ44 (44-pin Plastic Quad Flat Package)

XC17V08
8 Mbit
3.3V

PC44 (44-pin Plastic Chip Carrier)
VQ44 (44-pin Plastic Quad Flat Package)

XC17V16
16 Mbit
3.3V

PC44 (44-pin Plastic Chip Carrier)
VQ44 (44-pin Plastic Quad Flat Package)

Once you have selected the required target configuration device, click OK to accept the selection and exit the dialog. The status display icon for the Make PROM File entry will change to red (file missing). To generate the PROM file, simply click on the Make PROM File text – the status display icon will change to blue (running the command) and then eventually green, once the PROM file has been generated.

A report file for the operation (FPGAProjectName.prm) can be accessed by clicking on the associated icon, located to the right of the Make PROM File entry.

The generated PROM file (FPGAProjectName.mcs) is stored in a folder with the same name as the configuration used for the associated project. This folder is located in accordance with the output path defined in the Options tab of the Options for Project dialog (Project » Project Options).

Note: The configuration file can be generated with the Devices view in Not Live mode. This mode could be used if you just wanted to generate PROM files for one or more configuration devices, without going on to program any of the physical devices – configuration and/or FPGA – thereafter.

Accessing Configuration Device Information
Erasing the Configuration Device

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