Wishbone Probe Instrument
The Summer 09 release of Altium Designer sees the introduction of a new Wishbone Probe instrument (WB_PROBE). This instrument is a Wishbone Master that essentially allows you to tap into a Wishbone bus and 'probe' any of the Wishbone-compliant slave devices connected to it. It allows you to view and/or modify the content of registers in peripherals, and the memory space in memory devices, from its run-time panel, without having to use a processor instrument or source level debugger. It is particularly useful when you are using Wishbone without a processor!
Once your design is processed and downloaded to the target FPGA device, the Wishbone Probe instrument is accessed in the same way as any other instrument – simply double-click on its icon, in the Soft Devices chain of the Devices view (View»Devices View).
Use the Address control on the instrument panel to 'dial-up' the base address of a connected slave device, and subsequent addresses for internal registers (I/O Peripherals) or memory locations (memory devices). Click on the ... button to the right of the control to access the Wishbone Address dialog, which you can use to enter an address directly.
The Data window shows the current value, in hex format, for the data stored at the selected address. Click on the ... button to the right of the control to access the Wishbone Data dialog, which you can use to enter a new data value to be written to that address. The new data will be written upon clicking OK.
Click on the Show Panel button to access a panel from which you can view and modify the contents of registers and memory locations for the connected slave devices on the Wishbone bus. The panel has the same familiar look and feel as those memory view panels you will have become accustomed to seeing in relation to a processor in a design – and with much the same functionality. Use the panel to jump to a particular Wishbone address and view/modify the data as required.