WB_UART8_V2 - Pin Description
The following pin description is for the WB_UART8_V2 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_UART8_V2 pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock |
| RST_I | I | High | External (system) reset |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_UART8_V2 (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 4 | Address bus, used to select an internal register of the device for writing to/reading from |
| DAT_O | O | 8 | Data to be sent to host processor |
| DAT_I | I | 8 | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| INT_O | O | 2/High | Interrupt output lines. Two interrupts are sent to the connected host processor on this 2-bit bus: bit 0: set High if any of the lower 4 bits of the Status register (STATUS.3..STATUS.0) go High, and the corresponding interrupt enable bit is also High (in the Interrupt Mask register). These bits are all related to the transmitter. bit 1: set High if any of the upper 4 bits of the Status register (STATUS.7..STATUS.4) go High, and the corresponding interrupt enable bit is also High (in the Interrupt Mask register). These bits are all related to the receiver. |
| Serial Interface Signals | |||
| TXD | O | - | Serial data transmit |
| RXD | I | - | Serial data receive |
| CTS | I | Level | Clear To Send. Part of the automatic hardware-controlled handshake. 0 – device connected to the WB_UART8_V2 on the serial side is ready to receive data. Note: If the ctsen bit in the Line Control register (LINECTRL.0) is cleared, transmission will not depend on the readiness of the connected (remote) serial device. |
| RTS | O | Level | Request To Send. Part of the automatic hardware-controlled handshake. This output will follow the value of the rtsval bit in the Line Control register (LINECTRL.2), if the forcerts bit in the same register (LINECTRL.1) is High. The output will be Low only if the rtsval bit is Low and the specified high watermark in the RXHIGHMARK register has not been passed. Logically, this can be summarized as: RTS = (forcerts AND rtsval) OR ((NOT forcerts) AND RXHIGHMARK) |