WB_UART8_V2 - Operational Overview

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After an external reset, the WB_UART8_V2 is effectively ready for use straight away. The hardware controlled handshaking is disabled after a reset – meaning that if data is available in the Transmit Buffer, the device will start sending it, regardless of the state of the CTS pin. The Receiver will start receiving data as soon as the connected remote station sends it.

Hardware Handshaking

It is quite possible that the WB_UART8_V2 sends more data than the remote station's receiver can cope with and vice-versa. In this case, some sort of control is required to halt the transmission of data in either direction. The WB_UART8_V2 provides automatic, hardware controlled handshaking – commonly referred to as RTS/CTS handshaking.

Automatic hardware handshaking is enabled by setting the ctsen bit of the Line Control register (LINECTRL.0).

When the remote station is ready to receive data, the WB_UART8_V2's CTS input goes Low. The WB_UART8_V2 is free to transmit provided this input remains Low.

When the WB_UART8_V2 is ready to receive, it sets its RTS line Low. The remote station will continue to transmit data as long as this output is Low. The WB_UART8_V2 can control this output automatically, based on the defined watermark levels for the Receive Buffer, or manually using the forcerts and rtsval bits in the Line Control register (LINECTRL.1 and LINECTRL.2 respectively).


After a reset of the WB_UART8_V2, you may want to initialize the device and set it up ready in accordance with design requirements. Initialization can include:

  • Enabling hardware handshake by setting the ctsen bit in the Line Control register.
  • Writing the required values to the watermark registers (TXLOWMARK, RXHIGHMARK, RXLOWMARK).
  • Enabling the required interrupt bits in the Interrupt Mask register.
  • Loading the required receive delay time value into the Receive Delay Timeout register.
  • Loading the required inter character delay time value – for transmission – into the Inter Character Delay register.
  • Writing the required clock divisor value to the Baud Rate Generator register.

The Baud Rate Generator register should be written last, as doing so will actively clear all buffers – therefore resetting to a known state.

Data Transfer

On the transmitter side, the WB_UART8_V2 sends a logical '0' on its TXD line to notify the remote station's receiver that a new data word is being sent. The next byte of data in the Transmit Buffer is loaded into the Transmit Shift register (TX_SHIFT).

When writing to the Serial Data Buffer register (SBUF) address, the WB_UART8_V2 sends the following:

  • Start bit (implicitly '0')
  • 8 data bits
  • Stop bit (implicitly '1')

When writing to the BREAK register address, the WB_UART8_V2 sends a BREAK status, with a minimum of 10 '0' bits transmitted. The actual length of the BREAK is determined by the value written to the register.

On the receiver side, the WB_UART8_V2 looks for a logical '0' on its RXD line, to signify the start of data transmission from the remote station's transmitter. The 8 bits of data are then read into the Receive Shift register (RX_SHIFT) on each rising edge of the Receiver's clock. Once the Stop bit has been detected, the byte of data in the shift register is loaded into the Receive Buffer.

The WB_UART8_V2 and the connected remote station should ideally be operating at the same Baud rate. The receiver in either station uses the start bit of each transmission to synchronize its clock to that of the transmitter.

The WB_UART_V2's RXD line is delayed by two clock cycles – using two front-end flip-flops (internal to the peripheral) – in order to address signal stability issues. The output of the second of these flip-flops is fed into a state machine that looks for the falling edge of the Start bit. Once the Start bit is detected, the state machine then checks, at timed intervals, for subsequent data bit values.

If another byte of data is ready for transmission, the start bit of the next word is transmitted as soon as the stop bit of the previous word has been sent and the inter-character delay time has elapsed.

When there is nothing to transmit, the TXD line remains at logical '1'.

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