WB_TSPENDOWN - Pin Description

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Modified by Admin on Sep 13, 2017

The following pin description is for the WB_TSPENDOWN when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signal will be made available as a sheet entry, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_TSPENDOWN pin description.

Name	Type	Polarity/ Bus size	Description
Control Signals
CLK_I	I	Rise	External (system) clock signal
RST_I	I	High	External (system) reset
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_TSPENDOWN (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
DAT_O	O	16	Data to be sent to host processor
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
Interface Signal to the AD7483 Touch Screen Digitizer
PENDOWN	I	Low	Pen Down signal. Sourced from the AD7483 device's `\PENIRQ` output, this signal is used to alert the processor that the TFT LCD panel's touch screen has been touched. The state of this signal is reflected by the internal `pdreg` variable.