WB_SPI - Pin Description

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Modified by Admin on Sep 13, 2017

The following pin description is for the WB_SPI component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_SPI pin description.

Name	Type	Polarity/ Bus size	Description
Control Signals
CLK_I	I	Rise	External (system) clock signal
RST_I	I	High	External (system) reset. If this signal is active for at least one full cycle of the external clock signal (CLK_I), all internal registers will be reset.
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated.
ADR_I	I	3	Address bus, used to select an internal register of the device for writing to/reading from.
DAT_O	O	32	Data to be sent to host processor.
DAT_I	I	32	Data received from host processor.
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
SPI Bus Interface Signals
SPI_DOUT	O	-	Serial Data Out. This data is sent from the host processor to the target SPI device resource.
SPI_DIN	I	-	Serial Data In. This is data received from the target SPI device resource, to be sent to the host processor.
SPI_CLK	O	-	Serial Clock. This signal is generated by the Controller and is used to clock data in and out during communication with the target SPI device resource.
SPI_MODE	O	Level	Serial Mode. This signal is used to switch between the following two modes of access: 0 = Communicate directly with a slave device over the SPI bus 1 = Communicate with the NB2DSK01's SPI Controller, resident within the NanoTalk Controller Spartan-3 FPGA. More specifically, access is made to an 8-bit SPI device address register therein, which is used to store the address of the required SPI slave device you wish to communicate with. Writing to this register is the only means by which the design may be granted access to the SPI bus. The level of this signal is controlled directly by the `mode` bit in the Control register (CTRL.2).
SPI_CS	O	Level	Serial Chip Select. Take this signal Low to enable communications with the target SPI device, once the address for that device has been sent to the NanoBoard's SPI Controller, access to the SPI Bus has been granted, and the mode of access has been switched to direct communications (SPI_MODE taken Low). The level of this signal is controlled directly by the `cs` bit in the Control register (CTRL.1).