WB_SHARED_MEM_CTRL Configuration - Synchronous DRAM Settings

Clicking on the Synchronous DRAM entry in the left-hand pane of the Configure Memory Controller dialog will open the Synchronous DRAM page, as shown in Figure 1.

Figure 1. Configuration options when interfacing to Synchronous DRAM.

The following sections detail each of the configuration options available.

Memory Size

Use this region of the page to specify the size of the physical memory that you are interfacing to. For example, the common-bus SDRAM on a 3-connector daughter board is provided by two high-speed CMOS SDRAM devices. Each device is 256Mbit, organized as 16M x 16 bits (4M x 16 bits x 4 banks) – combined together to give 16M x 32-bit storage (64MByte).

The width of the SDRAM_ADR_I input line will automatically change in accordance with the memory size specified.

Table 1 lists the supported memory sizes and the corresponding size of the address lines (SDRAM_ADR_I and MEM_A) for each supported memory layout. Bear in mind that MEM_A can only be seen to change as depicted in the Table, if the option to show unused pins is disabled and Synchronous DRAM is the only memory type enabled.

Memory Layout

Use the drop-down available in this region of the page to select the layout for the physical memory:

• 1 x 32-bit Wide Device

• 1 x 16-bit Wide Device

• 1 x 8-bit Wide Device

• 2 x 16-bit Wide Devices

• 2 x 8-bit Wide Devices

In addition to determining the interface pinout for connection to the physical memory device(s), the memory layout also determines the number of rows and columns used to address the memory that the Controller will be working with.

Timing Settings

This region of the page allows you to specify timing related settings with respect to access of the physical SDRAM.

The first setting – SDRAM Clock Frequency in MHz – is used to specify the speed of the memory you are working with. The frequency of the signal arriving at the Controller's MEM_CLK input must equal the value specified by this setting. This clock frequency is used to calculate reload values for internal refresh cycle counters. The refresh is performed every 15.4µs.

The remaining settings are used to determine memory timing protocols, with each setting specified in terms of cycles of the MEM_CLK signal.

• CAS Latency (tCL) – the delay, in clock cycles, between the SDRAM device registering a Read access and the availability of the first piece of output data. This is typically set to 2 or 3 clock cycles (Default = 3 cycles).

• Load Mode Register To Activate (tMRD) – the minimum number of cycles that must be observed after the Mode register has been loaded, before the start of an access to memory (a particular row of a bank is opened for access). (Default = 2 cycles).

• Active to Read or Write delay (tRCD) – the minimum number of clock cycles that must be observed between the start of an access to memory (a particular row of a bank is opened for access) and the Read or Write actually being performed. (Default = 2 cycles).

• Auto Refresh period (tRFC) – the number of clock cycles required for the SDRAM device to perform one Auto Refresh cycle. (Default = 2 cycles).

• Precharge command period (tRP) – the number of clock cycles required to perform a precharge, which is simply the closing of the open row in a specific bank or the open row in all banks. During a precharge, the bank(s) will be idle and no Read or Write access is permitted. (Default = 2 cycles).

• Write Recovery time (tWR) – the minimum number of clock cycles between registration of the last required data element in a Write access and the start of a subsequent precharge for that row/bank. (Default = 2 cycles).