WB_SHARED_MEM_CTRL Configuration - Parallel Flash Settings

Clicking on the Parallel Flash entry in the left-hand pane of the Configure Memory Controller dialog will open the Parallel Flash page, as shown in Figure 1.

Figure 1. Configuration options when interfacing to parallel Flash memory.

The following sections detail each of the configuration options available.

Memory Size

Use this region of the page to specify the size of the physical memory that you are interfacing to. Only a single size is supported, allowing for connection to the common-bus Flash memory on a 3-connector daughter board. This memory is provided by a single 16-bit device organized as 16M x 16 bits (32MByte).

Memory Layout

As the Flash memory on a 3-connector daughter board is provided by a single 16-bit device, only one memory layout is supported – 1 x 16-bit Wide Device.

In addition to determining the interface pinout for connection to the physical memory device, the memory layout also determines the number of accesses required to Read or Write a single 32-bit word.

Timing Settings

This region of the page enables you to specify additional clock cycles (cycles of FLASH_CLK_I) to be added for each stage of a Read and Write operation. Each stage must be at least one clock cycle.

The minimum number of clock cycles for each operation are as follows:

• Read – two clock cycles. If the system clock (FLASH_CLK_I) is 50MHz, this equates to 40ns.

• Write – three clock cycles. With a system clock (FLASH_CLK_I) of 50MHz, this equates to 60ns.

The following default timing settings are used:

• Clock cycles for address setup – 6 cycles

• Clock cycles for write pulse – 6 cycles

• Clock cycles for post-write address hold – 6 cycles.