WB_SHARED_MEM_CTRL Configuration - General Settings

Figure 1. General settings for the Shared Memory Controller.

The General page of the Configure Memory Controller dialog provides options for configuring the graphical nature of the component, as well as clock synchronization when interfacing to SDRAM. The following sections discuss the various options on this page.

Graphical Attributes

This region of the page provides options to specify in which order the enabled memory interfaces (on the processor side) appear on the component's symbol. By default, the interfaces are arranged as follows:

• Top – SRAM interface (slave port S when placed in an OpenBus System)

• Middle – SDRAM interface (slave port SD when placed in an OpenBus System)

• Bottom – Parallel Flash interface (slave port F when placed in an OpenBus System)

When the component is placed on a schematic sheet, you can also define the separation between interfaces, by specifying the amount of extra space to be inserted after an interface's bank of pins.

Figure 2. Default interface order for schematic and OpenBus Shared Memory Controller components.

An option to control the visibility of unused pins for the Controller's physical memory interface – Show unused pins – is also provided. By default, this option is enabled and all pins of the interface will be shown. However, you may not be using all three memory types in your design. This option allows you to hide the 'clutter' of pins associated with memory types that are not being used.
 

 
Consider for example, using the Shared Memory Controller to access only the common-bus SRAM on a 3-connector daughter board. Let us assume also, that the memory layout is 2x16-bit devices, with a physical memory size of 1MB (256K x 32-bit). Figure 3 illustrates the physical memory interface for a Controller, placed on a schematic sheet, when the option to show unused pins is enabled (left) and disabled (right). See how the MEM_A line has changed to 17..0, reflecting the width used for addressing just the SRAM component of the shared memory architecture.

Figure 3. Physical memory interface for a Shared Memory Controller placed on a schematic and connecting
to common-bus SRAM only. On the left, the option to show unused pins is enabled; on the right it is disabled.

When placing the Controller in an OpenBus System, the option effects the corresponding sheet entries for the physical memory interface, that are added to the sheet symbol on the top-level schematic (Figure 4).

Figure 4. Physical memory interface for a Shared Memory Controller placed in an OpenBus System and connecting
to common-bus SRAM only. On the left, the option to show unused pins is enabled; on the right it is disabled.

In terms of wiring, it is more convenient to leave all interface pins visible (Show unused pins option enabled) and wire all pins to the corresponding ports of the SHARED_MEM_DAUGHTER port component. Those signals not required for the design, in accordance with the Controller's configuration, are internally handled. For example, active Low outputs relating to unused memory types are tied to '1', unused inputs are ignored and, if not using the SDRAM, the associated clock output signal will be tied to '0'.

If you do disable the Show unused pins option, you will need to place the port component that truly corresponds to the memory you are wishing to access, only wiring from the Shared Memory Controller to those pins of relevance. For the remaining pins of the port component chosen, use the orange guidance text on each unused port to terminate it correctly:

• VCC – connect the unused port to VCC

• GND – connect the unused port to GND

• X – place a No ERC directive on the unused port.

Figure 5 illustrates an example of using the Shared Memory Controller to access the SRAM and Flash memory on a daughter board. In this case, the SHARED_SRAM_FLASH_DAUGHTER port component has been used, with signals related to the SDRAM terminated accordingly.
 

 

Figure 5. Using a specific memory port component to interface to SRAM and Flash memory only. The port component provides guidance
on how to terminate unused pins.

Wishbone - Memory Clock Synchronization Scheme

This region of the dialog allows you to define the synchronization scheme to be used when interfacing to SDRAM. The following three options allow you to specify the relationship between the MEM_CLK input – the frequency of which is the same as the speed of memory you are using – and the external system clock, CLK_I – input to the processor and used as the Wishbone clock.

• Independent clocks – use this option when the memory is being clocked at a higher speed than the FPGA design. This option provides flexibility when debugging a design, as you can use any frequency for CLK_I (provided it's lower than MEM_CLK). However time is lost, in terms of data throughput, performing a resync between the Wishbone interface and the memory controller.

• Memory clock 2x Wishbone clock, synchronized on positive edge – use this option when the memory is being clocked at twice the speed of the FPGA design (e.g. SDRAM running at 100MHz and system clock for the design (CLK_I) is 50MHz). Time is still lost when performing a resync, but the resync is preformed faster due to prior knowledge of the relationship between the clocks. You can slow down the design clock, but this will result in the memory becoming slower too.

• Same clock – use this option when the memory is being clocked at the same speed as the FPGA design. This option is typically for slower FPGA devices, which can not be clocked as high as 100MHz. No resync is required between the Wishbone interface and the memory controller.