WB_SHARED_MEM_CTRL Configuration - Asynchronous SRAM Settings

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Modified by Admin on Sep 13, 2017

Clicking on the Asynchronous SRAM entry in the left-hand pane of the Configure Memory Controller dialog will open the Asynchronous SRAM page, as shown in Figure 1.

Figure 1. Configuration options when interfacing to asynchronous SRAM.

The following sections detail each of the configuration options available.

Memory Size

Use this region of the page to specify the size of the physical memory that you are interfacing to. For example, the common-bus SRAM on a 3-connector daughter board is provided by two 4Mbit, high-speed CMOS SRAM devices. Each device is organized as 256K x 16 bits – combined together to give 256K x 32-bit storage (1MByte).

The width of the SRAM_ADR_I input line will automatically change according to memory size specified.

Table 1 lists the supported memory sizes and the corresponding size of the address lines (SRAM_ADR_I and MEM_A) for each supported memory layout. Bear in mind that MEM_A can only be seen to change as depicted in the Table, if the option to show unused pins is disabled and Asynchronous SRAM is the only memory type enabled.

Table 1. SRAM size selection and effect on address size.

SRAM Size	Address Bus Sizing for each Memory Layout
	1 x 8-bit		2 x 8-bit		1 x 16-bit		2 x 16-bit		1 x 32-bit
	ADR_I	MEM_A	ADR_I	MEM_A	ADR_I	MEM_A	ADR_I	MEM_A	ADR_I	MEM_A
1KB	10	10	10	9	10	9	10	8	10	8
2KB	11	11	11	10	11	10	11	9	11	9
4KB	12	12	12	11	12	11	12	10	12	10
8KB	13	13	13	12	13	12	13	11	13	11
16KB	14	14	14	13	14	13	14	12	14	12
32KB	15	15	15	14	15	14	15	13	15	13
64KB	16	16	16	15	16	15	16	14	16	14
128KB	17	17	17	16	17	16	17	15	17	15
256KB	18	18	18	17	18	17	18	16	18	16
512KB	19	19	19	18	19	18	29	17	19	17
1MB	20	20	20	19	20	19	20	18	20	18
2MB	21	21	21	20	21	20	21	19	21	19
4MB	22	22	22	21	22	21	22	20	22	20
8MB	23	23	23	22	23	22	23	21	23	21
16MB	24	24	24	23	24	23	24	22	24	22

Memory Layout

Use the drop-down available in this region of the page to select the layout for the physical memory:

1 x 32-bit Wide Device

1 x 16-bit Wide Device

1 x 8-bit Wide Device

2 x 16-bit Wide Devices

2 x 8-bit Wide Devices

In addition to determining the interface pinout for connection to the physical memory device(s), the memory layout also determines the number of accesses required to Read or Write a single 32-bit word.

Timing Settings

This region of the page enables you to specify additional clock cycles (cycles of SRAM_CLK_I) to be added for each stage of a Read and Write operation. Each stage must be at least one clock cycle.

The minimum number of clock cycles for each operation are as follows:

Read – two clock cycles. If the system clock (SRAM_CLK_I) is 50MHz, this equates to 40ns.

Write – three clock cycles. With a system clock (SRAM_CLK_I) of 50MHz, this equates to 60ns.

The following default timing settings are used:

Clock cycles for address setup – 1 cycle

Clock cycles for write pulse – 1 cycle

Clock cycles for post-write address hold – 1 cycle.