WB_SDHC - Accessible Internal Registers
Contents
- Clock Divider Register (CDIV)
- Control Register (CTRL)
- Status Register (STAT)
- Command Transmitter Command Register (CMD_TXCMD)
- Command Transmitter Argument Register (CMD_TXARG)
- Command Receiver Size Register (CMD_RXSIZE)
- Command Receiver FIFO Interface (CMD_RXFIFO)
- Data Block Size Register (DAT_BLKSIZE)
- Data Transfer Size Register (DAT_RXSIZE)
- DMA Address Register (DAT_MEMADR)
- Version and Configuration Register (VERSION_INFO)
The following sections detail the internal registers for the SDHC Controller that can be accessed from the host processor.
Clock Divider Register (CDIV)
Address: 00h
Access: Read/Write
Size: 10 bits
Reset value: 0
This 10-bit register divides the system clock by 2 x (CDIV+1). If set to 0, the clock stops.
Control Register (CTRL)
Address: 01h
Access: Read/Write
Size: 6 + 2 bits (see below)
Reset value: 00
Bit | Access | Name | Function |
|---|---|---|---|
0 | Write Only | RESET | Reset the core |
1 | Read/Write | CMD_TXENABLE | Enable command transmitter |
2 | Read/Write | CMD_RXENABLE | Enable command receiver |
3 | Read/Write | DAT_TXENABLE | Enable data transmitter |
4 | Read/Write | DAT_RXENABLE | Enable data command receiver |
5 | Read/Write | ENDIANESS | DMA endianess (0 = big endian, 1 = little endian) |
30 | Write Only | RSTMASK | Only reset bits in the control register |
31 | Write Only | SETMASK | Only set bits in the control register |
If you set bit 31 when writing to the control register, bits are not reset. If you set bit 30 when writing to the control register, the bits you have set to '1' are actually reset in the control register.
Bits 0..4 are automatically reset by the hardware.
The software platform driver for the WB_SDHC will automatically toggle the ENDIANESS bit to the required value based on the endianess of the CPU used in the design, for example big-endian for TSK3000 or little-endian for Nios.
Status Register (STAT)
Address: 02h
Access: Read only
Size: 16 bits
Reset value:
Bit | Access | Name | Function |
|---|---|---|---|
0 | Read Only | SD_DETECT | Status of SD_DETECT pin |
1 | Read Only | SD_PROTECT | Status of SD_PROTECT pin |
2 | Read/Write | SD_REMOVED | Set by hardware if card has been removed, write '1' to reset |
3 | Read Only | CMD_TXENABLE | Command transmitter enable |
4 | Read Only | CMD_TXBUSY | Command transmitter is busy |
5 | Read Only | CMD_RXENABLE | Command receiver enable |
6 | Read Only | CMD_RXBUSY | Command receiver is busy |
7 | Read Only | CMD_RXFULL | Command receiver FIFO is full |
8 | Read Only | CMD_RXEMPTY | Command receiver FIFO is empty |
9 | Read Only | CMD_CRCERR | Command receiver CRC error detected |
10 | Read Only | DAT_TXENABLE | Data transmitter enable |
11 | Read Only | DAT_TXBUSY | Data transmitter is busy |
12 | Read Only | DAT_RXENABLE | Data receiver enable |
13 | Read Only | DAT_RXBUSY | Data receiver is busy |
14 | Read Only | DMA_TIMEOUT | DMA under- or over-run |
15 | Read Only | DAT_CRCERR | CRC detected in data receiver or reported by card |
16 | Read Only | DAT_READY | Ready/busy status from SD Card |
The "enable" bits indicate a transfer is requested and may be partially underway (check against "busy" to know if the transmission is running).
Command Transmitter Command Register (CMD_TXCMD)
Address: 03h
Access: Read/Write
Size: 8 bits
Write the command you want to transmit on the CMD line to this register before actually starting the transmission.
Command Transmitter Argument Register (CMD_TXARG)
Address: 04h
Access: Read/Write
Size: 32 bits
Write the payload you want to transmit on the CMD line to this register before actually starting the transmission.
Command Receiver Size Register (CMD_RXSIZE)
Address: 05h
Access: Read/Write
Size: 8 bits
The value in this register defines how many bytes are expected in the command response on the CMD line, excluding the CRC. Set this register before starting the actual transmission.
Command Receiver FIFO Interface (CMD_RXFIFO)
Address: 06h
Access: Read only
Size: 8 bits
This register is the interface to the command receive FIFO. Reading from it will return the first byte in the FIFO and update the read index counter.
Data Block Size Register (DAT_BLKSIZE)
Address: 07h
Access: Read/write
Size: 16 bits
Write the block length (in bytes) to be used for data communication with the SD Card into this register prior to starting data reception or transmission. Usually, the value set here will be 512.
Data Transfer Size Register (DAT_RXSIZE)
Address: 0x08
Access: Read/write
Size: 20 bits (see VERSION_INFO register)
Set the total number of data bytes to be transmitted or received into this register (excluding CRC).
DMA Address Register (DAT_MEMADR)
Address: 0x09
Access: Read/Write
Size: 20 bits (see VERSION_INFO register)
This register contains the address in which data is written to when receiving or from which data is fetched when transmitting. The least significant two bits of this register (1..0) should always be 0.
Version and Configuration Register (VERSION_INFO)
Address: 0Fh
Access: Read only
Size: 32 bits
This register can be read to obtain information on the version of the WB_SDHC peripheral and some configuration information:
Bits | Contents | Description |
|---|---|---|
31..24 | 11h | Core version identifier (e.g. 11h = core version1.1) |
16 | 0 | Endianess (0 = big endian, 1 = little endian). This bit follows the ENDIANESS bit in the Control register. |
15..8 | 10h | Command receiver FIFO size, in bytes |
7..0 | 14h | Size of memory address bus, in bits. This is equal in size to the DAT_RXSIZE and DAT_MEMADR registers. |