WB_PWM8, WB_PWMX - Interrupts

After a counter overflow event occurs, the INT_O pin will be asserted after one cycle of the external clock signal (CLK_I). This will only occur provided that:

• the global interrupt enable bit (pien) is set High in the Control register (PWCON.1) and

• the relevant interrupt enable bit is set High for the PWM Counter (pwie) and/or Pre-Scaler Counter (prie) in the Control register (PWCON.3 and PWCON.2 respectively).

When the host controller clears all interrupt flags in the PWCON register, the INT_O pin will go low on the next rising edge of CLK_I. If the pien interrupt enable flag is cleared, then the INT_O pin will go low immediately when the command is sampled on the Wishbone interface (on the first rising edge of CLK_I after the command has been presented to the device).