WB_PWM8 - Pin Description
Frozen Content
The following pin description is for the WB_PWM8 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Name | Type | Polarity / Bus size | Description |
---|---|---|---|
Control Signals | |||
CLK_I | I | Rise | External system clock |
RST_I | I | High | External system reset |
Host Processor Interface Signals | |||
STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_PWM8 Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
ADR_I | I | 2 | Standard Wishbone address bus, used to select an internal register of the Wishbone slave device for writing to/reading from. |
DAT_O | O | 8 | Data to be sent to an external Wishbone master device (e.g. host processor) |
DAT_I | I | 8 | Data received from an external Wishbone master device (e.g. host processor) |
WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
INT_O | O | High | Interrupt signal. Used to alert the host to the presence of a counter overflow event. This can occur when either the PWM Counter or Pre-scaler Counter counts past zero. Each interrupt source is individually enabled. |
Outputs | |||
PWMP | O | High | Differential Pulse-Width-Modulated rectangular wave output signal. PWMP = positive side of signal |
PWMN | O | Low |