WB_PWM8 - Accessible Internal Registers

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The following sections detail the internal registers for the WB_PWM8 that can be accessed from the host processor.

Pulse Width Register (PWMRG)

Address: 0h

Access: Read/Write

Value after Reset: 00h

This register holds the value (00h to FFh) of the desired pulse width. 00h is full-off and FFh is full-on, with a linear variation in-between. The value in this register can be anywhere in the valid range 0 to 2 8 - 1.

Prescaler Counter Reload Low Register (PWPLO)

Address: 1h

Access: Read/Write

Value after Reset: 00h

This register holds the Low Byte of the 16-bit Pre-scaler Counter reload value. The value in this register can be anywhere in the valid range 0 to 2 8 - 1.

Prescaler Counter Reload High Register (PWPHI)

Address: 2h

Access: Read/Write

Value after Reset: 00h

This register holds the High Byte of the 16-bit Pre-scaler Counter reload value. The value in this register can be anywhere in the valid range 0 to 2 8 - 1.

Control Register (PWCON)

This register is used to enable the device and configure the overflow interrupts.

Table 1. The PWCON register.
MSB                                                                                                                                                                                                                LSB
7
6
5
4
3
2
1
0
pwi
pri
pfl1
pfl0
pwie
prie
pien
pwen


Table 2. The PWCON register bit functions.
Bit
Symbol
Function

PWCON.7

pwi*

PWM Counter Interrupt flag. This bit is set by hardware when the 8-bit PWM counter overflows (counts past zero) and must be cleared by writing a zero to it from software.

PWCON.6

pri*

Pre-Scaler Counter Interrupt flag. This bit is set by hardware when the 16-bit Pre-scaler counter overflows (counts past zero) and must be cleared by writing a zero to it from software.

PWCON.5

pfl1

Spare bit. Can be used as a general purpose flag.

PWCON.4

pfl0

Spare bit. Can be used as a general purpose flag.

PWCON.3

pwie

PWM Counter Interrupt Enable bit:

0 = pwi will not generate an interrupt assertion on INT_O.
1 = pwi will generate an interrupt assertion on INT_O.

PWCON.2

prie

Pre-Scaler Counter Interrupt Enable bit:

0 = pri will not generate an interrupt assertion on INT_O.
1 = pri will generate an interrupt assertion on INT_O.

PWCON.1

pien

Global Interrupt Enable bit:

0 = None of the enabled interrupts will cause INT_O to be asserted.
1 = All of the enabled interrupts will cause INT_O to be asserted.

PWCON.0

pwen

Global Controller Enable bit:

0 = No overflow interrupts can occur and both outputs are at logic zero. The pre-scaler will continue to count down but will not be reloaded with the value stored in registers PWPHI and PWPLO.
1 = The Controller is operational and outputs are enabled. Counter overflows are registered by the pwi and pri bits and INT_O will be asserted if either interrupt is enabled when the corresponding counter overflow has occurred.

* These flags will register a counter overflow even if the interrupt has been disabled. This allows for the checking of overflows in software, so processors that do not have interrupt capabilities can still use the WB_PWM8 for precise timing.

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