WB_OWM - Pin Description

Frozen Content

Modified by Admin on Sep 13, 2017

The following pin description is for the device when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_OWM pin description.

Name	Type	Polarity/Bus size	Description
Control Signals
CLK_I	I	Rise	External (system) clock signal
RST_I	I	High	External (system) reset
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_OWM (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
ADR_I	I	3	Address bus, used to select an internal register of the device for writing to/reading from
DAT_O	O	8	Data to be sent to host processor
DAT_I	I	8	Data received from host processor
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
INT_O	O	Level	Interrupt output line. An external interrupt to the processor can be generated on this line if one or more of six possible interrupt flags become set in the Interrupt register, and the corresponding enable bit in the Interrupt Enable register is also set. The active level of the `INT_O` pin is determined by the `ias` bit in the Interrupt Enable register (INTEN.1): INTEN.1 = '0' – `INT_O` is active Low INTEN.1 = '1' – `INT_O` is active High By default, after an external reset or after reading the Interrupt register, the `ias` bit will be cleared, resulting in the `INT_O` becoming active Low.
1-Wire Interface Signals
DQ_EN	O	High	Output enable signal for the 1-Wire data bidirectional buffer
DQ_OUT	O	-	Serial data output
DQ_IN	I	-	Serial data input

Note: To simplify using the bidirectional DQ bus, the WB_OWM includes a bus pin for each direction, allowing them to be wired independently.