WB_OWM - Operational Overview

The following sections summarize initialization of the WB_OWM Controller, detection of slave devices on the 1-Wire bus, and sending and receiving of data over the bus.

Initialization

After an external reset, you will need to initialize the WB_OWM. This should be carried out in accordance with design requirements and can include:

• Loading the Clock Divider register with a value that will divide the external system clock (CLK_I) down to the required 1MHz clock.

• Configuring the interrupt sources for presence detection. This is achieved by writing 03h to the Interrupt Enable register. This value configures the INT_O line to be active High by setting the ias bit, and sets the epd bit.

• Clearing any pending interrupts. This is achieved by performing a read of the Interrupt and Data registers (the latter reading the Receive Buffer).

Device Detection

Once the WB_OWM has been initialized, detection of a slave device attached to the 1-Wire bus is performed as follows:

• Issue a reset of the 1-Wire bus by writing a '1' to the 1wr bit in the Command register (CMD.0).

• Wait for the INT_O line to be taken High. This will happen after the bus reset has completed and enough time has elapsed for slave devices to flag their presence (by issuing a presence pulse). The cause of the interrupt – the pd bit in the Interrupt register (INT.0) – will become set at this time.

• Read the Interrupt register. The result of the detection will be loaded into the pdr bit (INT.1), with a '0' signifying the presence of (one or more) slave devices. The pd bit will be cleared as a result of reading the Interrupt register.

Device Identification

Before being able to communicate with a specific slave device on the 1-Wire bus, the processor needs to identify exactly which devices are connected to the bus. This is achieved by conducting a search ROM algorithm, which essentially allows the processor to identify the unique 64-bit ID stored in each slave device's ROM.

The following is a simple overview of the steps involved in obtaining the ROM IDs of each slave device on the bus:

• Setup interrupts (ias, erbf, etbe and epd set to '1')

• Clear pending interrupts by reading the Interrupt and Data registers.

• Issue a reset of the 1-Wire bus

• After the presence detect interrupt is encountered, write the Search ROM command value to the bus (F0h).

• Place the WB_OWM into Search ROM Accelerator mode (by setting the sra bit in the Command Register (CMD.2)).

• Transmit the 16 byte search value based on the last ROM ID found. Each byte is transmitted in turn, and the received data read once the processor is interrupted by the rbf flag in the Interrupt register becoming set. For the initial search each byte will be 00h.

• The 16 bytes received back from the bus are processed (through use of a Recover ROM routine) to obtain the true 8 byte ROM ID for a device, and to generate the required transmit values for the 16 bytes used to conduct the next search pass.

• The search continues until a duplicate ROM ID is obtained – signaling that all devices attached to the 1-Wire bus have been identified.

For information regarding communications when the WB_OWM is configured to operate in Search Accelerator mode, and an example of a ROM search, refer to the data sheet for the underlying Controller (DS1WM.pdf) available at www.maxim-ic.com.

Addressing a Particular Slave Device

Once the processor "knows" all of the devices present on the 1-Wire bus, it can send commands and data to all devices, or it can choose to communicate with a specific, individual device. This is achieved by sending the Match ROM command (55h) followed by the 8-byte ROM ID for the slave device you wish to communicate with. Once addressed, the processor can send data to, and receive data from, just this device – all other slave devices on the bus will ignore communications until the next reset of the 1-Wire bus is issued.

Data Transfer over the 1-Wire Bus

Once the required slave device is detected and addressed, data can be sent to, and received from, that device. The following sections detail the write and read processes.

Sending Data to a Slave Device

Prior to actually sending the data, setup any interrupt sources as required. This could involve setting the etbe and/or etemt bits in the Interrupt Enable register (INTEN.2 and INTEN.3 respectively). It is a good idea to clear all pending interrupts as well, by reading both the Interrupt and Data registers.

The data (ROM command) to be sent to the slave device can then be written to the Data register – which will load the data byte directly into the Transmit Buffer. From here, it is moved into the Transmit Shift register and then shifted serially onto the 1-Wire bus – LSB first.

The tbe bit in the Interrupt register will become set once the byte of data has been moved from the Transmit Buffer to the Transmit Shift register. Provided the etbe bit in the Interrupt Enable register has been set, this will interrupt the processor, alerting it to the fact that it is ready to accept the next byte of data for transmission.

If the Transmit Shift register has become empty (all 8 bits shifted out onto the 1-Wire bus), the temt bit in the Interrupt register will become set. If the etemt bit in the Interrupt Enable register is set, the processor will be interrupted and alerted to this state.

By writing the next byte of data to the Transmit Buffer, the tbe interrupt will be cleared. Once this data is moved into the Transmit Shift register, the temt interrupt will be cleared, and the tbe interrupt will occur once again.

Receiving Data from a Slave Device

Prior to receiving data, setup any interrupt sources as required. This typically involves setting the erbf bit in the Interrupt Enable register (INTEN.4). It is a good idea to clear all pending interrupts as well, by reading both the Interrupt and Data registers.

A read is initiated by the host processor writing the value FFh to the Transmit Buffer. The data shifted from the 1-Wire bus into the Receive Shift register is the wired AND of the transmitted FFh byte and the byte of data sent from the slave device. Once the full 8 bits of data are in the Receive Shift register, the data is automatically moved into the Receive Buffer, from where it can be read by the processor.

The rbf bit in the Interrupt register will become set once the byte of data has been moved into the Receive Buffer. Provided the erbf bit in the Interrupt Enable register has been set, this will interrupt the processor, alerting it to the fact that there is data for it to read and process. The rbf interrupt will be cleared once the processor reads the Receive Buffer.

The value FFh must be sent in order to read each additional byte of data. If the slave device does not send a byte of data – due to not being ready for whatever reason – the value read will simply be the FFh that was transmitted to initiate the read.