WB_MEM_CTRL Configuration - Block RAM Settings
When the chosen memory type is Block RAM, the Configure (Memory Controller) dialog will appear as shown in Figure 1.
Figure 1. Configuration options when interfacing to BRAM.
The following sections detail each of the configuration options available.
Size of Block RAM Array
Use this region to specify the size of the physical RAM that you are interfacing to. The width of the BRAM interface address bus and also the ADR_I input line will update accordingly upon leaving the dialog.
Table 1 lists the supported BRAM sizes and the corresponding size of the address buses for each configuration of Controller.
Table 1. BRAM size selection and effect on address size.| RAM Size | Address Bus Sizing | |
| ADR_I | BRAM_A | |
| 1Kb | 10 | 8 |
| 2Kb | 11 | 9 |
| 4Kb | 12 | 10 |
| 8Kb | 13 | 11 |
| 16Kb | 14 | 12 |
| 32Kb | 15 | 13 |
| 64Kb | 16 | 14 |
| 128Kb | 17 | 15 |
| 256Kb | 18 | 16 |
| 512Kb | 19 | 17 |
| 1Mb | 20 | 18 |
| 2Mb | 21 | 19 |
| 4Mb | 22 | 20 |
| 8Mb | 23 | 21 |
| 16Mb | 24 | 22 |
Memory Layout
This region of the dialog is non-editable and reflects the layout of physical BRAM that can be connected to the Controller – in this case a single 1 x 32-bit wide device.
Clock Cycles for Reading and Writing
These two regions of the dialog are non-editable. They reflect the number of clock cycles required to perform a read or write operation respectively.
Reading
Two clock cycles are required for a zero wait-state read, which equates to 40ns for a 50MHz system clock (CLK_I).
Writing
Three clock cycles are required for each write operation, which equates to 60ns for a 50MHz system clock (CLK_I). These three cycles can be broken down into the following stages:
- 1 clock cycle for address set-up
- 1 clock cycle for write pulse
- 1 clock cycle for post-write address hold.