WB_MEM_CTRL Configuration - Asynchronous SRAM Settings

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Modified by Admin on Sep 13, 2017

When the chosen memory type is Asynchronous SRAM, the Configure (Memory Controller) dialog will appear as shown in Figure 1.

Figure 1. Configuration options when interfacing to SRAM.

The following sections detail each of the configuration options available.

Size of Static RAM Array

Use this region to specify the size of the physical RAM that you are interfacing to. The width of the SRAM interface address bus(es) and also the ADR_I input line will update accordingly upon leaving the dialog.

Table 1 lists the supported SRAM sizes and the corresponding size of the address buses for each configuration of the Memory Controller.

Table 1. SRAM size selection and effect on address size.

SRAM Size	Address Bus Sizing for each Memory Layout
	1 x 8-bit		2 x 8-bit		1 x 16-bit		2 x 16-bit		1 x 32-bit
	ADR_I	SRAM_A	ADR_I	SRAM_A	ADR_I	SRAM_A	ADR_I	SRAM0_A SRAM1_A	ADR_I	SRAM_A
1KB	10	10	10	9	10	9	10	8	10	8
2KB	11	11	11	10	11	10	11	9	11	9
4KB	12	12	12	11	12	11	12	10	12	10
8KB	13	13	13	12	13	12	13	11	13	11
16KB	14	14	14	13	14	13	14	12	14	12
32KB	15	15	15	14	15	14	15	13	15	13
64KB	16	16	16	15	16	15	16	14	16	14
128KB	17	17	17	16	17	16	17	15	17	15
256KB	18	18	18	17	18	17	18	16	18	16
512KB	19	19	19	18	19	18	29	17	19	17
1MB	20	20	20	19	20	19	20	18	20	18
2MB	21	21	21	20	21	20	21	19	21	19
4MB	22	22	22	21	22	21	22	20	22	20
8MB	23	23	23	22	23	22	23	21	23	21
16MB	24	24	24	23	24	23	24	22	24	22

Memory Layout

Use the drop-down available in this region of the dialog to select the layout for the physical memory:

1 x 32-bit Wide Device

1 x 16-bit Wide Device

1 x 8-bit Wide Device

2 x 16-bit Wide Devices

2 x 8-bit Wide Devices.

The symbol for the placed Memory Controller will automatically be updated to reflect your selection, upon leaving the dialog.

In addition to determining the interface pinout for connection to the physical memory device(s), the memory layout also determines the number of accesses required to read or write a single 32-bit word.

Clock Cycles for Reading and Writing

These two regions of the dialog are non-editable. They reflect the number of clock cycles required to perform a read or write operation respectively.

Reading

Two clock cycles are required for a zero wait-state read, which equates to 40ns for a 50MHz system clock (CLK_I).

Writing

Three clock cycles are required for each write operation, which equates to 60ns for a 50MHz system clock (CLK_I). These three cycles can be broken down into the following stages:

1 clock cycle for address set-up

1 clock cycle for write pulse

1 clock cycle for post-write address hold.